Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2004-02-10
2008-12-16
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07467341
ABSTRACT:
An object of the invention is to provide a boundary scan controller that allows a boundary scan to be executed and also allows a semiconductor apparatus to be manufactured in such a manner that the same type of semiconductor circuit chips are stacked. When identification data stored in memory means (85) is compared with fixed data held in fixed-data holding means (87) by comparison means (88) and the identification data is coincident with the fixed data, a data derivation section (89) outputs the same data as data which is outputted from an output section (86). In a boundary scan test, a data derivation section (89) of a boundary controller (80) provided for each semiconductor circuit chip is connected to the same bus line. When the identification data is not coincident with the fixed data, the data derivation section (89) can be substantially disconnected from the bus line. In this way, the same type of semiconductor circuit chips for which the boundary controller (80) is provided can be stacked, thereby manufacturing the semiconductor apparatus.
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International Preliminary Report on Patentability for PCT Application No. PCT/JP2004/001430 mailed on Feb. 13, 2006, six pages.
Britt Cynthia
Morrison & Foerster / LLP
Radosevich Steven D
Sharp Kabushiki Kaisha
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