Boundary scan circuit

Details Boundary scan circuit Boundary scan circuit

2006-04-18

2006-04-18

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07032147

ABSTRACT:
An electronic device includes a first circuit, a second circuit, and a boundary scan circuit. The boundary scan circuit includes a boundary scan register having a first cell connected to an input node of the first circuit, and a second cell connected between an output node of the first circuit and an input node of the second circuit. The second cell has a latch flip-flop. The boundary scan circuit also includes an interface that enables and disables the latching operation of the latch flip-flop according to an input instruction code. While the latching operation is disabled, the output from the latch flip-flop to the second circuit remains unchanged. In this state, the boundary scan circuit can be used to test the first circuit without unintended effects on the second circuit.

REFERENCES:
patent: 6073254 (2000-06-01), Whetsel
patent: 6804725 (2004-10-01), Whetsel
patent: 2001/0037480 (2001-11-01), Whetsel
patent: 05-093762 (1993-04-01), None

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