Boride electrodes and barriers for cell dielectrics

Details Boride electrodes and barriers for cell dielectrics Boride electrodes and barriers for cell dielectrics

2001-08-30

2003-02-11

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000, C438S396000

Reexamination Certificate

active

06518121

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to integrated circuits and more particularly to the use of transition metal boride materials for electrodes and barrier layers to protect cell dielectrics in capacitors for such circuits.
BACKGROUND OF THE INVENTION
Capacitors are used in a wide variety of integrated circuits. Capacitors are of special concern in DRAM (dynamic random access memory) circuits; therefore, the invention will be discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in other types of memory circuits, such as SRAMs, as well as any other circuit in which cell dielectrics are used.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most basic form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor.
There is continuous pressure in the industry to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including trench and stacked capacitors.
Stacked capacitors are capacitors which are stacked, or placed, over the access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the present invention will be discussed in connection with stacked capacitors, but should not be understood to be limited thereto.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube (cylinder) with an oval or circular cross section. The wall of the tube consists of two electrodes, i.e., two plates of conductive material, such as doped polycrystalline silicon (referred to herein as polysilicon or poly), separated by a dielectric. A preferred dielectric is tantalum pentoxide (Ta
2
O
5
). The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open. The sidewall and closed end of the tube form a container; hence the name “container capacitor.” Although the invention will be further discussed in connection with stacked container capacitors, the invention should not be understood to be limited thereto.
The electrodes in a DRAM cell capacitor must be conductive, and must protect the dielectric film from interaction with interlayer dielectrics (e.g., BPSG) and from the harsh thermal processing encountered in subsequent steps of DRAM process flow. For example, Ta
2
O
5
dielectrics may be used for high density DRAMs such as 64 Mbit and 256 Mbit DRAMs, because chemical vapor deposition (CVD) of Ta
2
O
5
provides a high dielectric constant (≈25) and good step coverage. However, the ability of Ta
2
O
5
and other high dielectrics to withstand high temperature processes, such as the BPSG reflow process after capacitor formation, is the most serious hurdle to overcome in the application of these dielectrics to the DRAM process.
Kwon, K. W. et al., “Degradation-Free Ta
2
O
5
Capacitor After BPSG Reflow at 850° C. for High Density DRAMs,” IEDM 93-53 (1993 IEEE), refers to a Ta
2
O
5
capacitor having a TiN/poly-Si top electrode which exhibited low leakage current after BPSG reflow at 850° C. The TiN top electrode was coated with a barrier layer of poly-Si to protect the underlying Ta
2
O
5
dielectric during the high temperature reflow. However, TiN from organic precursors, e.g., ((CH
3
N)
2
)
4
Ti, has a relatively high resistivity, and thus is not particularly well-suited for high performance devices.
What is needed is a thermally robust capacitor which maintains good electrode conductivity and frequency response. The capacitor electrodes must offer a combination of good barrier properties (to protect the dielectric film), and good conductivity to improve the frequency response of the capacitor and minimize depletion effects.
SUMMARY OF THE INVENTION
The present invention provides boride barrier layers to protect cell dielectrics such as Ta
2
O
5
, SrTiO
3
(“ST”), (Ba, Sr)TiO
3
(“BST”), Pb(Z,Ti)O
3
(“PZT”), SrBi
2
Ta
2
O
9
(“SBT”) and Ba(Zr,Ti)O
3
(“BZT”) against dielectric degradation through thermal effects and interaction with surrounding materials. TiB
x
(x=1 to 3), ZrB
x
(x=1 to 3) and HfB
x
(x=1 to 3) layers provide excellent barrier protection, and good conductivity as capacitor electrodes, and so may be employed either as capacitor electrodes, or as separate barrier layers formed adjacent to conventional capacitor electrodes, either atop these electrodes or interposed between the electrode and the capacitor dielectric.


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K. W. Kwon et al., “Degradation-Free Ta2O5Capacitor After BPSG Reflow at 850° C for High Density DRAMSs”, Advanced Technology Center, Samsung Electronics Co. 1993, pp. 3.5.1. to 3.5.3.

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