Borderless wordline for DRAM cell

Details Borderless wordline for DRAM cell Borderless wordline for DRAM cell

1998-03-31

2001-08-07

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S302000

Reexamination Certificate

active

06271555

ABSTRACT:

FIELD OF INVENTION
This invention relates generally to DRAM cell design using transistors and semiconductor interconnection techniques, and more particularly to a conductive wordline for a DRAM cell and a method of making the same wherein the bitline contact is borderless to the wordline which is especially useful in folded-bitline architecture for DRAMs.
BACKGROUND OF THE INVENTION
Large numbers of DRAM cells must be interconnected with wordlines, and wordlines and spaces between wordlines are a factor in determining the size of a folded-bitline cell. Typically, wordlines are formed as thin films of a conductor, such as aluminum or polysilicon, deposited on insulating materials on the semiconductor surface and defined as lines photolithographically. Efforts to shrink wordlines and the spaces between wordlines are limited since both line widths and spaces cannot photolithographically be made smaller than the line width, for example, decreasing the line width usually increases the line-to-line spacing and so the overall wordline pitch is not improved. The cost of decreasing the photolithographic minimum dimension is high, and each such effort has defined succeeding generations of semiconductor products. In each generation of DRAM cells, the photolithographically defined wordline and/or it's associated space have thus been formed at the photolithographic minimum dimension. Each such effort has defined succeeding generations of semiconductor products. In each generation of DRAM cells, the photolithographically defined wordline and/or its associated space have thus been formed at the photolithographic minimum dimension.
In the folded-bitline DRAM cell design, both an active and a passing wordline pass through each cell, as illustrated in commonly assigned U.S. Pat. No. 4,801,988 (“the '988 patent”), issued to D. M. Kenney, entitled “Semiconductor Trench Capacitor Cell with Merged Isolation and Node Trench Construction,” and shown therein which is incorporated herein by reference. Crossing over trench capacitors
505
A and
510
A for a pair of cells in
FIG. 1
, are wordlines
515
A and
520
A. The space required for such a DRAM cell is a minimum dimension for each of the two wordlines in each cell and an additional minimum dimension for each space between each wordline. Thus the total minimum length of the traditional folded bitline cell is
4
minimum dimensions. The width of the cell is at least two minimum dimensions, of which one is for the components in the cell and the other is for a thick isolation (a trench capacitor can be a part of this isolation) in the space between cells. Thus, the minimum area of a traditional cell has been 8 square minimum dimensions, or 8 squares.
One approach to avoid the photolithographic limit is to provide a wordline formed of a conductive sidewall rail. The width of such rails is determined by the thickness of the deposited conductor, and this thickness can be significantly less than a minimum photolithographic dimension. Commonly assigned U.S. Pat. No. 5,202,272 (“the '272 patent”), issued to Hsieh, entitled “Field Effect Transistor Formed With Deep-Submicron Gate,” and U.S. Pat. No. 5,013,680 (“the '680 patent”), issued to Lowrey, entitled “Process for Fabricating a DRAM Array Having Feature Widths that Transcend the Resolution Limit of Available Photolithography,” all of which are incorporated herein by reference, teach methods of using a subminimum dimension conductive sidewall spacer rail to form a wordline.
One problem encountered in the use of such subminimum dimension spacer rail wordlines is the difficulty of precisely controlling the length of the device and the extent of lateral diffusion of the source and drain. For example, small variations of spacer thickness or lateral diffusion can result in a large variation in the length of the subminimum dimension channel. The result can be large leakage currents on the one hand and degraded performance on the other. The present invention avoids the difficulties of the subminimum dimension sidewall spacer rail wordlines of the prior art.
Moreover, many prior art structures and techniques for sublithographic wordlines and/or bitlines do not provide a bitline contact which is borderless to the wordline.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a folded bitline DRAM cell with a photolithographically formed gate, the cell having an area of less than 8 squares with the bitline being borderless to the wordline. It is also a feature of the present invention that a minimum subdivision wordline makes approximately minimum individual gate segments with the bitline contact being borderless to the wordline.
It is still a further object of the present invention to provide a transistor with individual segment gate conductors and a subminimum dimension gate connector with the bitline contact being borderless to the wordline.
These and other objects of the invention are accomplished by a semiconductor structure comprising a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate electrodes. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.


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BU9-94-136—

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