Borderless interconnection process

Details Borderless interconnection process Borderless interconnection process

2005-04-12

2005-04-12

Thai, Luan (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S637000, C438S709000, C438S738000

Reexamination Certificate

active

06878639

ABSTRACT:
A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.

REFERENCES:
patent: 5286344 (1994-02-01), Blalock et al.
patent: 6265271 (2001-07-01), Thei et al.
patent: 6497993 (2002-12-01), Chiu et al.
patent: 378392 (2000-01-01), None
patent: 455983 (2001-09-01), None

Affiliated with

Also associated with

Rating

Borderless interconnection process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Borderless interconnection process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Borderless interconnection process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3439634