Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-10-11
2004-07-20
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S781000, C257S782000, C257S783000, C257S784000
Reexamination Certificate
active
06765228
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to packaging of semiconductor integrated circuits. More particularly, the present invention relates to a new and improved bonding pad having separate areas for probe needle contact and wire bonding in semiconductor packaging technology.
BACKGROUND OF THE INVENTION
One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic-ceramic packages and plastic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a plastic package, on the other hand, is not completely isolated from the ambient environment because the package is composed of an epoxy-based resin. Consequently, ambient air is able to penetrate the package and adversely affect the chip over time. Recent advances in plastic packaging, however, has expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical and mechanical interconnection of IC chips to other microelectronic devices. The solder bumps serve to both secure the IC chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board. The BGA technique is included under a broader connection technology known as “Controlled Collapse Chip Connection-C4” or “flip-chip” technology.
Flip chip technology can be used in conjunction with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. The solder bumps are typically located at the perimeter of the flip chip on electrically conductive bond pads that are electrically interconnected with the circuitry on the flip chip. Because of the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of solder bumps are often required. The size of a flip chip is typically on the order of about thirteen millimeters per side, resulting in crowding of the solder bumps along the perimeter of the flip chip. Consequently, flip chip conductor patterns are typically composed of numerous individual conductors that are often spaced apart about 0.1 millimeter or less.
Wirebonding is the most common technique for establishing electrical connection between the bonding pads on the surface of a chip or die and the inner lead terminals, or posts, on the leadframe or substrate. A section of a typical conventional wirebonded chip
26
is shown schematically in FIG.
1
and may include multiple wire bonding balls
10
, each of which is directly bonded to the continuous upper surface of a bonding pad
14
, typically rectangular in configuration, as shown in
FIG. 1A
, and partially covered by a passivation layer
12
. A pad opening
13
in the passivation layer
12
exposes the bonding pad
14
, through which pad opening
13
the bonding ball
10
extends. The bonding pad
14
is surrounded by a dielectric layer
15
such as an oxide in the chip
26
. As further shown in
FIG. 1
, the bonding pad
14
is provided in electrical contact with an upper conductive layer
16
, which is separated from an underlying conductive layer
22
by an insulative layer
18
. The conductive layers
16
,
22
are disposed in electrical contact with each other through conductive vias
20
that extend through the insulative layers
18
. The various insulative layers
18
and conductive layers
22
are sequentially deposited on a silicon substrate
24
throughout semiconductor fabrication, in conventional fashion. Each bonding ball
10
connects a bonding wire
28
, through a lead
30
, to the terminals (not shown) on the leadframe or substrate (not shown), as shown in FIG.
2
.
As further shown in
FIG. 2
, the bonding pads
14
are typically arranged in rows which extend adjacent to respective edges of the chip
26
. Prior to packaging and formation of the bonding balls
10
on the respective bonding pads
14
, the chip
26
is subjected to parametric testing which utilizes test structures to assess the electrical characteristics and reliability of the devices on the wafer. Probe cards are typically used as an interface between the devices on the chip and automated test equipment. The probe card typically includes a printed circuit board from which extends multiple probe needles
34
, each of which is disposed in electrical contact with the device through the respective bonding pads
14
, as shown in FIG.
3
. Each probe needle
34
typically contacts the approximate center of the bonding pad
14
at a pressure of typically about 2-3 grams. Consequently, the probe needle
34
typically forms a scrub mark
32
and a hump
33
of pad material in the center of the bonding pad
14
, as shown in FIG.
4
.
As further shown in
FIGS. 3 and 4
, the probe needle contact area
8
, which was contacted by the probe needle
34
in the testing step, substantially overlaps and typically circumscribes the wire bonding area
6
on the bonding pad
14
to which the bonding ball
10
is subsequently bonded in the packaging step. Due to the presence of the probe needle scrub mark
32
and the hump
33
in the surface of the bonding pad
14
, such an overlap area between the wire bonding area
6
and the probe needle contact area
8
on the bonding pad
14
reduces the effective bonding area for the bonding ball
10
on the bump pad
14
. This decreased bonding area for the bonding ball
10
tends to reduce effective bonding of the bonding ball
10
to the bonding pad
14
. Accordingly, there is an established need for a new layout for a bonding pad which provides separate test probing and ball or wire bonding areas on the bonding pad.
An object of the present invention is to provide a new and improved layout for a bonding pad for IC (integrated circuit) chips.
Another object of the present invention is to provide a method which enhances wafer sort yield and productivity by relaxing probe mark specifications in the testing of chips.
Still another object of the present invention is to provide a method for providing separate areas for test probing and bonding on a bonding pad and demarcating the areas during chip production.
Another embodiment of the present invention is to provide a new and improved bonding pad which enhances bonding of a solder bump or bond wire to the bump pad.
Still another embodiment of the present invention is to provide a new and improved bonding pad which provides a bonding area which is sufficiently large for effective bonding of a solder bump or bond wire to the bump pad.
Yet another object of the present invention is to provide a new and improved bonding pad which provides an intact bonding area for the bonding of a solder bump or a bond wire to the bonding pad.
Still another object of the present invention is to provide a new and improved bonding pad which is particularly advantageous for fine pitch pad design applications.
A still further object of the present invention is to provide a new and improved bonding pad which provides separate areas for probe needle con
Lin Kuan-Min
Shen Jin-Ji
Fahmy Wael
Ha Nathan W.
Taiwan Semiconductor Maunfacturing Co., Ltd.
LandOfFree
Bonding pad with separate bonding and probing areas does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bonding pad with separate bonding and probing areas, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bonding pad with separate bonding and probing areas will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3241943