Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
1999-12-10
2002-05-07
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S780000, C257S785000
Reexamination Certificate
active
06384486
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of semiconductor devices and processes, and more specifically to integrated circuits that permit wire bonding to be performed directly over portions of the active circuit area.
DESCRIPTION OF THE RELATED ART
Two independent trends in semiconductor technology, both with a long history, contribute to the urgency for the present invention. The first trend concerns aspects of manufacturing cost savings by conserving semiconductor “real estate”.
In order to accommodate balls of bonding wires or solder, typical bonding pads on silicon integrated circuits ICs) have to be of sufficient size; they typically range from squares of 80×80 &mgr;m to squares of 150×150 &mgr;m. They consume, therefore, an area between approximately 1 and 20% of the circuit area, dependent on the number of bonding pads and the size of the integrated circuit. For manufacturing and assembly reasons, the bonding pads are arranged in rows along the periphery of the circuit, usually stringed along all four chip sides.
Until now, all semiconductor devices manufactured had to exclude the area covered by the bonding pads from use for laying out actual circuit patterns because of the high risk of damaging the circuit structures due to the unavoidable forces needed in the bonding process. Evidently, considerable savings of silicon real estate can be obtained if circuit patterns could be allowed to be laid out under the bonding pad metal. One way to achieve this would be to create another level of metallization dedicated solely to bonding pad formation. This level would be built over a protective overcoat covering an active circuit area. In existing technology, however, a special stress buffer layer of polyimide has to be applied between the protective overcoat and the extra metal layer, as shown by K. G. Heinen et al. (“Wire Bonds over Active Circuits”, Proc. IEEE 44th Elect. Comp. Tech. Conf., 1994, pp. 922-928). The cost of applying this polyimide layer has so far prohibited the implementation of the bonds-over-active-circuit concept.
Another approach in existing technology has been proposed in U.S. Patent Application No. 60/092,961, filed Jul. 14, 1998 (Saran, “System and Method for Bonding Over Active Integrated Circuits”). In order to make the bonding pads strong enough to withstand the mechanical forces required in the wire bonding process, reinforcing systems under the bonding pad are described which utilize specific portions of the actual IC as the means to reinforce weak dielectric layers under the bonding pad. This method requires specific design or redesign of the IC and is poorly suited for standard linear and logic ICs which often have numerous bonding pads but relatively small circuit areas.
The second trend concerns certain processes in the assembly of a semiconductor chip. It is well known that bonding pads in silicon ICs can be damaged during wafer probing using fine-tip tungsten needles, further during conventional thermosonic wire bonding to aluminum metallization on the circuits, or during solder ball attachment in chip-to-substrate devices of more recent assembly developments. In wire bonding, particularly suspect are the mechanical loading and ultrasonic stresses applied the tip of the bonding capillary to the bonding pad. When the damage is not apparent during the bonding process, the defects may manifest themselves subsequently by succumbing to thermo-mechanical stresses generated during the plastic encapsulation, accelerated reliability testing, temperature cycling, and device operation. The damage appears in most cases as microcracks which may progress to fatal fractures in the underlying dielectric material, as chip-outs of brittle or mechanically weak dielectric films, often together with pieces of metal or silicon, or as lifted ball bonds, or as delamination of metal layers.
Recent technological developments in the semiconductor technology tend to aggravate the problem. For instance, newer dielectric materials such as silicon-containing hydrogen silsesquioxane (HSQ) are being preferred due to their lower dielectric constant which helps to reduce the capacitance C in the RC time constant and thus allows higher circuit speeds. Since lower density and porosity of dielectric films reduce the dielectric constant, films with these characteristics are introduced even when they are mechanically weaker. Films made of aerogels, organic polyimides, and parylenes fall into the same category. These materials are mechanically weaker than previous standard insulators such as the plasma-enhanced chemical vapor deposited dielectrics. Since these materials are also used under the bonding pad metal, they magnify the risk of device failure by cracking.
In addition, the spacing between bonding pads is being progressively reduced to save valuable silicon real estate. Consequently, the bonding parameters have to become more aggressive to achieve stronger bonds in spite of the smaller size. Bonding force and ultrasonic energy during bonding are being increased. Again, the risk of yield loss and lowered reliability is becoming greater.
For conventional bonding pad metallization processes, a solution to the aforementioned problems was disclosed in U.S. patent application Ser. No. 08/847,239, filed May 1, 1997 (Saran et al., “System and Method for Reinforcing a Bond Pad”). Some concepts and methods of this disclosure have been subsequently described by M. Saran et al. in a publication entitled “Elimination of Bond-pad Damage through Structural Reinforcement of Intermetal Dielectrics” (Internat. Reliab. Physics Symp., March 1998). In essence, a metal structure designed for mechanical strength serves as a reinforcement for the mechanically weak dielectric layer. The metal is deposited and then etched to form “reservoirs” to be filled with the dielectric material, for example HSQ. Since HSQ is deposited by a spin-on process, the sizes of the reservoirs have to remain large enough to be filled controllably with the dielectric. This requirement is contrary to the industry trend for continued shrinking of all circuit feature sizes.
When the insulator film is formed first, openings such as trenches are etched into this film; metal such as copper or aluminum is then deposited to fill these openings, while metal deposited elsewhere on the surface is removed grinding and polishing (so-called damascene metallization process). Wire bonding and solder ball flip-chip bonding over damascene metal pads are facing the same risks of cracking weak dielectric layers as in the case of conventional metallization. U.S. Patent Application No. 60/085,876, filed May 18, 1998 (Saran et al., “Fine Pitch System and Method for Reinforcing Bond Pads in Semiconductor Devices”) teaches the design and fabrication process for metal structures made with the damascene technique reinforcing weak dielectrics under the bonding pads.
An urgent need has therefore arisen for a low-cost, reliable mass production system and method providing the manufacture of wire and solder ball bonds directly over active IC areas. The system should provide stress-free, simple, and no-cost-added contact pads for flexible, tolerant bonding processes even when the contact pads are situated above one or more structurally and mechanically weak dielectric layers. The system and method should be applicable to a wide spectrum of design, material and process variations, leading to significant savings of silicon, as well as to improved process yield and device reliability. Preferably, these innovations should be accomplished using the installed process and equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
According to the present invention for semiconductor integrated circuits (ICs), at least a portion of a contact pad can be positioned over the IC, when a combination of a bondable metal layer, a stress-absorbing metal layer, and a mechanically strengthened, electrically insulating layer, separate the contact pad and the portion of the IC, pro
Ciani Samuel A.
Zuniga Edgar R.
Cruz Lourdes
Honeycutt Gary C.
Lee Eddie
Navarro Arthur I.
Telecky Fred
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