Body-tied-to-body SOI CMOS inverter circuit

Details Body-tied-to-body SOI CMOS inverter circuit Body-tied-to-body SOI CMOS inverter circuit

2002-10-31

2003-10-07

Pham, Long (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S479000

Reexamination Certificate

active

06630376

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to silicon-on-insulator (SOI) technology and, more particularly, to a complementary metal oxide semiconductor (CMOS) inverter for use in SOI circuit design.
BACKGROUND OF THE INVENTION
Complementary metal oxide semiconductor (CMOS) devices that are produced in mass quantities are referred to as “bulk” CMOS. This is because such devices include a semiconductive bulk substrate on which active or passive circuit elements are disposed.
Recently, silicon-on-insulator (SOI) CMOS devices have been introduced which consume less power than do bulk CMOS devices. SOI devices are characterized by a thin layer of insulator material (a so-called buried oxide layer, or “BOX” layer) that is sandwiched between a bulk substrate and an active semiconductor layer. The circuit elements of the device are formed in the active semiconductor layer insulated from the bulk substrate by the BOX layer. Typically, no other layers of material are interposed between the BOX insulator layer and the bulk substrate.
In an SOI CMOS device, the circuit elements in the active semiconductor layer are established by regions which are doped as appropriate with N-type or P-type conductivity dopants. For example, for an N-channel transistor, the active semiconductor layer will include a gate element disposed over a body region having a P-type dopant, with the body region being disposed between a source region and a drain region, each of which are doped with an N-type dopant. These devices provide an important advantage in many applications such as battery-powered mobile telephones and battery-powered laptop computers. Also, SOI CMOS devices advantageously operate at higher speeds than do bulk CMOS devices. SOI CMOS architecture eliminates inherent parasitic circuit elements in bulk CMOS due to junction capacitances between adjacent components. Also, CMOS circuits are very fast, due to the fact that the bulk capacitance is very small. SOI CMOS is also immune to latchup.
Problems surrounding the technology include the SOI floating-body effect. This particular problem has been addressed by others, by example, in a paper entitled “Suppression of the SOI Floating-body Effects by Linked-Body Device Structure,” by W. Chen, et. al., 1996 Symposium on VLSI Technology Digest of Technical Papers.
The core of CMOS circuit designs is an inverter circuit consisting of a linked pair of complementary transistors. A CMOS integrated circuit may literally include millions of such inverters. Unfortunately, the aforementioned floating-body effect has been found to affect detrimentally the operation of an inverter circuit. For example, excess carriers within the complementary transistors tend to accumulate due to the floating body. As a result, the output of the inverter circuit has been found to exhibit a hysteresis effect. Such hysteresis is problematic in that it can reduce significantly the acceptable switching rate of the device, for example.
In view of the aforementioned shortcomings associated with CMOS inverter circuits in SOI devices, there exists a strong need in the art for an SOI CMOS inverter circuit which exhibits reduced hysteresis effects. More generally, there is a strong need in the art for an SOI CMOS inverter circuit which is less susceptible to detrimental operation due to the floating-body.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a semiconductor-on-insulator (SOI) inverter circuit is provided. The inverter circuit includes a bulk substrate, an insulator layer formed on a surface of the substrate, an active semiconductor layer formed on a surface of the insulator layer opposite the substrate, a p-type body region and an n-type body region formed generally adjacent one another in the active semiconductor layer, an n-channel metal-on-semiconductor field effect transistor (MOSFET) formed in the p-type body region and a p-channel MOSFET formed in the n-type body region, wherein a gate of each of the n-channel MOSFET and the p-channel MOSFET are electrically coupled to form an input of the inverter circuit and a drain of each of the n-channel MOSFET and the p-channel MOSFET are electrically coupled to form an output of the inverter, a p-type body tie region formed in the active semiconductor layer immediately adjacent the p-type body region and an n-type body tie region formed in the active semiconductor layer immediately adjacent the n-type body region; and an electrically conductive element electrically coupling the p-type body tie region to the n-type body tie region.
In accordance with another aspect of the invention, a method of manufacturing a semiconductor-on-insulator (SOI) inverter circuit is provided. The method includes the steps of forming an insulator layer on a surface of a bulk substrate, forming an active semiconductor layer on a surface of the insulator layer opposite the substrate, forming a p-type body region and an n-type body region generally adjacent one another in the active semiconductor layer, forming an n-channel metal-oxide-semiconductor field effect transistor (MOSFET) in the p-type body region and a p-channel MOSFET in the n-type body region, wherein a gate of each of the n-channel MOSFET and the p-channel MOSFET are electrically coupled to form an input of the inverter circuit and a drain of each of the n-channel MOSFET and the p-channel MOSFET are electrically coupled to form an output of the inverter, forming a p-type body tie region in the active semiconductor layer immediately adjacent the p-type body region and an n-type body tie region in the active semiconductor layer immediately adjacent the n-type body region, and providing an electrically conductive element electrically coupling the p-type body tie region to the n-type body tie region.


REFERENCES:
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patent: 5693975 (1997-12-01), Lien
patent: 5914515 (1999-06-01), Fukumoto et al.
patent: 6429492 (2002-08-01), Rockett
patent: 6456157 (2002-09-01), Forbes et al.
patent: 99/33115 (1999-07-01), None
Chapter 2 entitled “Cmos Fabrication Technology And Design Rules” of Design of VLSI Systems; pp. 1-16.
What is SOI—Silicon Genesis—SiGen Corp.

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