4. Electronic digital logic circuitry
  5. Interface
  6. Logic level shifting

Julian C. Gradinariu

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Block redundancy in ultra low power memory circuits

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Circuit to provide a time delay

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate

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Input buffer with stabilized trip points

Electronic digital logic circuitry – Interface – Logic level shifting
Patent

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Profile ID: LFUS-PAI-P-1825597

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