Block matching processor and method for block matching...

Details Block matching processor and method for block matching... Block matching processor and method for block matching...

2006-07-18

2006-07-18

Rao, Andy (Department: 2613)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C375S240170, C348S721000

Reexamination Certificate

active

07079579

ABSTRACT:
There is provided a block matching processor and method for flexibly supporting block matching motion estimation at motion vector prediction modes using matching blocks of various sizes. Each of difference unit (D-unit) arrays takes each smallest size matching block, calculates the difference between the pixels of a current frame and the pixels of a reference frame, and converts the differences to absolute values. An accumulator generates SADs (Sum of Absolute Difference) for the smallest size matching blocks and SADs for all the matching blocks of various sizes by tree-like hierarchical addition of the absolute values of the smallest size matching blocks received from the D-unit arrays.

REFERENCES:
patent: 5604546 (1997-02-01), Iwata
patent: 5696836 (1997-12-01), Yoshino et al.
patent: 6414994 (2002-07-01), Hazra
patent: 6519005 (2003-02-01), Bakhmutsky et al.

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