Block contact architectures for nanoscale channel transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S283000

Reexamination Certificate

active

11173866

ABSTRACT:
A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

REFERENCES:
patent: 4906589 (1990-03-01), Chao
patent: 5124777 (1992-06-01), Lee
patent: 5338959 (1994-08-01), Kim et al.
patent: 5346839 (1994-09-01), Sundaresan
patent: 5391506 (1995-02-01), Tada et al.
patent: 5466621 (1995-11-01), Hisamoto et al.
patent: 5545586 (1996-08-01), Koh
patent: 5563077 (1996-10-01), Ha
patent: 5578513 (1996-11-01), Maegawa
patent: 5658806 (1997-08-01), Lin et al.
patent: 5701016 (1997-12-01), Burroughs et al.
patent: 5716879 (1998-02-01), Choi et al.
patent: 5793088 (1998-08-01), Choi et al.
patent: 5827769 (1998-10-01), Aminzadeh et al.
patent: 5888309 (1999-03-01), Yu
patent: 5905285 (1999-05-01), Gardner et al.
patent: 6163053 (2000-12-01), Kawashima
patent: 6252284 (2001-06-01), Muller et al.
patent: 6307235 (2001-10-01), Forbes et al.
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6383882 (2002-05-01), Lee et al.
patent: 6396108 (2002-05-01), Krivokapic et al.
patent: 6407442 (2002-06-01), Inoue et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6413877 (2002-07-01), Annapragada
patent: 6457890 (2002-11-01), Yu
patent: 6475869 (2002-11-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6645797 (2003-11-01), Buynoski et al.
patent: 6680240 (2004-01-01), Maszara
patent: 6706571 (2004-03-01), Yu et al.
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 6713396 (2004-03-01), Anthony
patent: 6716684 (2004-04-01), Krivokapic et al.
patent: 6716686 (2004-04-01), Buynoski et al.
patent: 6716690 (2004-04-01), Wang et al.
patent: 6730964 (2004-05-01), Horiuchi
patent: 6756657 (2004-06-01), Zhang et al.
patent: 6764884 (2004-07-01), Yu et al.
patent: 6790733 (2004-09-01), Natzle et al.
patent: 6794313 (2004-09-01), Chang
patent: 6835618 (2004-12-01), Dakshina-Murthy
patent: 6858478 (2005-02-01), Chau et al.
patent: 6884154 (2005-04-01), Mizushima et al.
patent: 6906151 (2005-06-01), Hareland et al.
patent: 6921982 (2005-07-01), Joshi et al.
patent: 7105894 (2006-09-01), Yeo et al.
patent: 2002/0011612 (2002-01-01), Hieda
patent: 2002/0036290 (2002-03-01), Inaba et al.
patent: 2002/0081794 (2002-06-01), Ito
patent: 2002/0166838 (2002-11-01), Nagarajan
patent: 2002/0167007 (2002-11-01), Yamazaki et al.
patent: 2003/0057486 (2003-03-01), Gambino
patent: 2003/0085194 (2003-05-01), Hopkins, Jr.
patent: 2003/0098488 (2003-05-01), O'Keeffe et al.
patent: 2003/0102497 (2003-06-01), Fried et al.
patent: 2003/0111686 (2003-06-01), Nowak
patent: 2003/0122186 (2003-07-01), Sekigawa et al.
patent: 2003/0143791 (2003-07-01), Cheong et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2003/0201458 (2003-10-01), Clark et al.
patent: 2003/0227036 (2003-12-01), Sugiyama et al.
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 2004/0036118 (2004-02-01), Adadeer et al.
patent: 2004/0036127 (2004-02-01), Chau et al.
patent: 2004/0070020 (2004-04-01), Fujiwara et al.
patent: 2004/0092062 (2004-05-01), Ahmed et al.
patent: 2004/0092067 (2004-05-01), Hanafi et al.
patent: 2004/0094807 (2004-05-01), Chau et al.
patent: 2004/0110097 (2004-06-01), Ahmed et al.
patent: 2004/0119100 (2004-06-01), Nowak et al.
patent: 2004/0126975 (2004-07-01), Ahmed et al.
patent: 2004/0166642 (2004-08-01), Chen et al.
patent: 2004/0180491 (2004-09-01), Arai et al.
patent: 2004/0191980 (2004-09-01), Rios et al.
patent: 2004/0195624 (2004-10-01), Liu et al.
patent: 2004/0198003 (2004-10-01), Yeo et al.
patent: 2004/0219780 (2004-11-01), Ohuchi
patent: 2004/0227187 (2004-11-01), Cheng et al.
patent: 2004/0238887 (2004-12-01), Nihey
patent: 2004/0256647 (2004-12-01), Lee et al.
patent: 2004/0262683 (2004-12-01), Nihey
patent: 2004/0262699 (2004-12-01), Rios et al.
patent: 2005/0035415 (2005-02-01), Yeo et al.
patent: 2005/0118790 (2005-06-01), Lee et al.
patent: 2005/0127362 (2005-06-01), Zhang et al.
patent: 2005/0145941 (2005-07-01), Bedell et al.
patent: 2005/0156171 (2005-07-01), Brask et al.
patent: 2005/0224797 (2005-10-01), Ko et al.
patent: 2005/0224800 (2005-10-01), Lindert
patent: 2006/0014338 (2006-01-01), Doris et al.
patent: 0 623 963 (1994-11-01), None
patent: 1 202 335 (2002-05-01), None
patent: 1 566 844 (2005-08-01), None
patent: 06177089 (1994-06-01), None
patent: 2003-298051 (2003-10-01), None
patent: WO 02/43151 (2002-05-01), None
patent: WO 2004/059726 (2004-07-01), None
V. Subramanian et al., “A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100m MOSFETS” Proceeding of the 57th Annual Device Research Conference, pp. 28-29 (1999).
Hisamoto et al., “A Folded-channel MOSFET for Deepsub-tenth Micron Era”, 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034 (1998).
Huang et al., “Sub 50-nm FinFET: PMOS”, 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70 (1999).
Auth et al., “Vertical, Fully-Depleted, Surroundings Gate MOSFETS On sub-0.1um Thick Silicon Pillars”, 1996 54th Annual Device Research Conference Digest, pp. 108-109 (1996).
Hisamoto et al., “A Fully Depleted Lean-Channel Transistor (DELTA)—A Novel Vertical Ultrathin SOI MOSFET”, IEEE Electron Device Letters, V. 11(1), pp. 36-38 (1990).
Jong-Tae Park et al., “Pi-Gate SOI MOSFET” IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, pp. 405-406.
Hisamoto, Digh et al. “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm”, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
International Search Report PCT/US 03/26242, 2004.
International Search Report PCT/US 03/39727, 2004.
International Search Report PCT/US 03/40320, 2004.
T. Park et al., “Fabrication of Body-Tied FinFETs (Omega MOSFETS) Using Bulk Si Wafers”, 2003 Symposia on VLSI Technology Digest of Technical Papers, Jun. 2003, pp. 135-136.
A. Burenkov et al., “Corner Effect in Double and Tripe Gate FinFets”, IEEE 2003, pp. 135-138.
S.T. Chang et al., “3-D Simulation of Strained Si/SiGe Heterojunction FinFETs”, pp. 176-177, 2003.
International Search Report PCT/US2005/010505, 2005.
International Search Report PCT/US2005/020339, 2005.
International Search Report PCT/US2005/000947 (7pages).
Jing Guo, et al. “Performance Projections for Ballistic Carbon Nanotube Field-Effect Transistors”, Applied Physics Letters, vol. 80, No. 17, pp. 3192-3194 (Apr. 29, 2004).
Ali Javey, et al., “High-K Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates”, Advance Online Publication, Published online, pp. 1-6 (Nov. 17, 2002).
Richard Martel, et al., “Carbon Nanotube Field Effect Transistors for Logic Applications” IBM, T.J. Watson Research Center, 2001 IEEE, IEDM 01, pp. 159-162.
David M. Fried, et al., “High-Performance P-Type Independent-Gate FinFETs, IEEE Electron Device Letters”, vol. 25, No. 4, Apr. 2004, pp. 199-201.
David M. Fried, et al., “Improved Independent Gate N-Type FinFET Fabrication and Characterization”, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 592-594.
Charles Kuo, et al. “A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications”, IEEE Transactions on Electron Devices, vol. 50, No. 12, Dec. 2003, pp. 2408-2416.
Charles Kuo, et al., “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications”, 2002 IEEE International Electron Devices Meeting Technical Digest, Dec. 2002, pp. 843-846.
Takashi Ohsawa, et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of

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