Block-by-block leakage control and interface

Details Block-by-block leakage control and interface Block-by-block leakage control and interface

2008-06-23

2010-06-01

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S112000, C326S119000

Reexamination Certificate

active

07728621

ABSTRACT:
In one embodiment, a method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays is provided wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherein each sub-array asserts a local clock if the sub-array is addressed. The method includes the act of asserting a sleep signal while addressing a given one of the sub-arrays such that only the given one of the sub-arrays is placed into the sleep mode.

REFERENCES:
patent: 7196960 (2007-03-01), Isoda et al.
patent: 2002/0079933 (2002-06-01), Degoirat et al.
patent: 2002/0158665 (2002-10-01), Ye et al.
patent: 2005/0146948 (2005-07-01), Hose, Jr. et al.
patent: 2006/0164904 (2006-07-01), Saleh
patent: 00/10820 (2000-11-01), None
patent: WO 00/67380 (2000-11-01), None

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