Blanket well counter doping process for high speed/low power MOS

Details Blanket well counter doping process for high speed/low power MOS Blanket well counter doping process for high speed/low power MOS

1998-03-23

1999-10-05

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438225, 438514, 438527, H01L 218238, H01L 21425

Patent

active

059637994

ABSTRACT:
The present invention is a blanket well counter doping process for high speed and low power MOSFETs. An N-well region and a P-well region are in a substrate and a pad silicon oxide layer is on the substrate. A silicon nitride pattern is formed on the pad oxide layer to define active regions of the N-well and P-well region, a field oxide region is formed by using the silicon nitride as a mask. Afterward, an N-type ion implantation is implemented for anti-punchthrough region of the N-well region. A blanket P-type ion implantation is performed for N-well counter doping and P-well doping. A P-type low-energy and low-dosage ions is then implanted into the substrate for the threshold voltage adjustment. The last implantation stage is N-type and low dose to form a P-well counter doping region and an N-well doping region. Finally, a gate structure is manufactured on the N-well region and the P-well region and source/drain regions are fabricated in the P-well region and the N-well region to form an NMOS device and a PMOS device.

REFERENCES:
patent: 5141882 (1992-08-01), Komori et al.
patent: 5283200 (1994-02-01), Okamoto
patent: 5290714 (1994-03-01), Onozawa
patent: 5399895 (1995-03-01), Koga
patent: 5464789 (1995-11-01), Saito
patent: 5516711 (1996-05-01), Wang
patent: 5693505 (1997-12-01), Kobayashi
patent: 5795801 (1998-08-01), Lee
patent: 5795803 (1998-08-01), Takamura et al.
patent: 5804846 (1998-09-01), Fuller
K.F. Lee et al., Room Temperature 0.1 .mu.m CMOS Technology with 11.8 ps Gate Delay, 1993 IEEE, pp. 131-134, no month given.
Ramune Nagisetty et al., A Novel Self-Aligned Punchthrough Implant: A Simulation Study, IEEE Transactions on Electron Devices, vol. 43, No. 8, Aug. 1996, pp. 1312-1314.
Hiroyuki Nakamura et al., A Self-Aligned Counter-Doped Well Process Utilizing Channeling Ion Implantation, IEEE Transactions on Electron Devices, vol. 43, No. 7, Jul. 1996, pp. 1099-1103.

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