Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1996-03-05
2000-05-23
Beck, Shrive
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
427 97, 427250, 427255, 4272557, 2041921, 20419217, B05D 512, C23C 1604, C23C 1606, C23C 1404
Patent
active
060663588
ABSTRACT:
The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of conducting layers to form continuous, void-free interconnects in sub-half micron, high aspect ratio aperture width applications and highly oriented conducting layers. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by physical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.
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Chen Fusen
Chen Liang
Guo Ted
Mosely Roderick C.
Applied Materials Inc.
Beck Shrive
Chen Bret
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