Bitline voltage stabilization device and method

Static information storage and retrieval – Read/write circuit – Including signal clamping

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Details

365196, 36523002, G11C 1604

Patent

active

059301783

ABSTRACT:
A voltage control circuit for maintaining voltage levels on a pair of bitlines at a desirable above ground voltage is disclosed herein. In an exemplary embodiment, a semiconductor storage device includes a plurality of pairs of bitlines; a p-type field effect transistor multiplexer (PMUX) connecting each bitline of the pair to a sense amplifier; and a clamping circuit which prevents voltage levels on the bitlines from dwelling below a predetermined minimum voltage level. A method is also disclosed herein in which voltage levels on a pair of bitlines are maintained at a desirable above ground voltage level by connecting each bitline of a pair to a sense amplifier through a p-type field effect transistor multiplexer (PMUX); and clamping each bitline to prevent the voltage level thereon from dwelling below a predetermined minimum voltage level.

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M. Asakura et al., "An Experimental 256-Mb DRAM with Boosted Sense-Ground Scheme", IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994.
T. Ooishi et al., "An Automatic Temperature Compensation of Internal Sense Ground . . . ", IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995.
S. H. Dhong et al., "Low-Power Sensing Scheme with a Limited Bit-line Swing and Bit-Line Multiplexing", IBM Technical Disclosure Bulletin, vol. 34, No. 9, Feb. 1992, pp. 449-450.

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