Bitline precharge

Details Bitline precharge Bitline precharge

2001-09-21

2003-01-07

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S154000

Reexamination Certificate

active

06504775

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM). In particular, the present invention relates to a circuit and method for high speed precharging of bitlines in an open bitline architecture CAM device.
BACKGROUND OF THE INVENTION
In many conventional memory systems, such as random access memory, binary digits (bits) are stored in memory cells, and are accessed by a processor that specifies a linear address that is associated with the given cell. This system provides rapid access to any portion of the memory system within certain limitations. To facilitate processor control, each operation that accesses memory must declare, as a part of the instruction, the address of the memory cell/cells required. Standard memory systems are not well designed for a content based search. Content based searches in standard memory require software based algorithmic search under the control of the microprocessor. Many memory operations are required to perform a search. These searches are neither quick nor efficient in using processor resources.
To overcome these inadequacies an associative memory system called Content Addressable Memory (CAM) has been developed. CAM allows cells to be referenced by their contents, so it has first found use in lookup table implementations such as cache memory subsystems and is now rapidly finding use in networking systems. CAM's most valuable feature is its ability to perform a search and compare of multiple locations as a single operation, in which search data is compared with data stored within the CAM. Typically search data is loaded onto search lines and compared with stored words in the CAM. During a search-and-compare operation, a match or mismatch signal associated with each stored word is generated on a matchline, indicating whether the search word matches a stored word or not. A typical word of stored data includes actual data with a number appended header bits, such as an “E” bit or empty bit for example, although the header bits are not specifically searched during search-and-compare operations.
A CAM stores data in a matrix of cells, which are generally either SRAM based cells or DRAM based cells. Until recently, SRAM based CAM cells have been most common because of their simple implementation. However, to provide ternary state CAMs, ie. where the search and compare operation returns a “0”, “1”or “don't care” result, ternary state SRAM based cells typically require many more transistors than a DRAM based cells. As a result, ternary state SRAM based CAMs have a much lower packing density than ternary DRAM cells.
A typical CAM block diagram is shown in FIG.
1
. The CAM
10
includes a matrix, or array
100
, of DRAM based CAM cells (not shown) arranged in rows and columns. An array of DRAM based ternary CAM cells have the advantage of occupying significantly less silicon area than their SRAM based counterparts. A predetermined number of CAM cells in a row store a word of data. An address decoder
17
is used to select any row within the CAM array
100
to allow data to be written into or read out of the selected row. Data access circuitry such as bitlines and column selection devices, are located within the array
100
to transfer data into and out of the array
100
. Located within CAM array
100
for each row of CAM cells are matchline sense circuits, which are not shown, and are used during search-and-compare operations for outputting a result indicating a successful or unsuccessful match of a search word against the stored word in the row. The results for all rows are processed by the priority encoder
22
to output the address (Match Address) corresponding to the location of a matched word. The match address is stored in match address registers
18
before being output by the match address output block
19
. Data is written into array
100
through the data I/O block
11
and the various data registers
15
. Data is read out from the array
100
through the data output register
23
and the data I/O block
11
. Other components of the CAM include the control circuit block
12
, the flag logic block
13
, the voltage supply generation block
14
, various control and address registers
16
, refresh counter
20
and JTAG block
21
.
FIG. 2
shows a typical ternary DRAM type CAM cell
140
as described in Canadian Patent Application No. 2,266,062, filed Mar. 31, 1999, the contents of which are incorporated herein by reference. Cell
140
has a comparison circuit which includes an n-channel search transistor
141
connected in series with an n-channel compare transistor
142
between a matchline ML and a tail line TL. A search line SL* is connected to the gate of search transistor
141
. The storage circuit includes an n-channel access transistor
143
having a gate connected to a wordline WL and connected in series with capacitor
144
between bitline BL and a cell plate voltage potential VCP. Charge storage node CELL
1
is connected to the gate of compare transistor
142
to turn on transistor
142
if there is charge stored on capacitor
144
i.e. if CELL
1
is logic “1”. The remaining transistors and capacitor replicate transistors
141
,
142
,
143
and capacitor
144
for the other half of the ternary data bit, and are connected to corresponding lines SL and BL* and are provided to support ternary data storage. Together they can store a ternary value representing logic “1”, logic “0”, or “don't care”.
Ternary Value
CELL1
CELL2
0
0
1
1
1
0
“Don't Care”
0
0
The tail line TL is typically connected to ground and all the transistors are n-channel transistors. The description of the operation of the ternary DRAM cell is detailed in the aforementioned reference.
As previously mentioned, memory array
100
uses DRAM type memory cells to attain a higher density of cells per unit area of silicon, which has the benefit of reducing the overall cost of manufacturing. However, within the field of DRAM memory, there are two well known architectures used for arranging the memory cells and bitlines, which when applied to the ternary CAM of the present invention, each provide distinct advantages and disadvantages to the CAM device.
The first architecture is the open bitline architecture, generally shown in FIG.
3
. The arrangement shown in
FIG. 3
is representative of the physical layout of the bitlines with respect to the bitline sense amplifier (BLSA) on a fabricated device. Wordlines, memory cells and read/write circuits are intentionally omitted to simplify the schematic. But it will be understood by those skilled in the art that wordlines would run perpendicular to the bitlines, memory cells would be located near the intersection between each wordline and bitline, and read/write circuits are coupled to the bitlines. Complementary bitlines
32
and
34
extend away from the left and right sides of the bitline sense amplifier (BLSA)
33
. A bitline sense amplifier such as BLSA
33
is well known in the art and typically includes a pair of cross-coupled complementary pair of CMOS transistors. An n-channel equalization transistor
31
is connected between bitlines
32
and
34
for electrically shorting the two bitlines together, and has a gate controlled by a bitline equalization signal BLEQ. Bitlines
32
and
34
, equalization transistor
31
and BLSA
33
form one open bitline pair. Another bitline pair consisting of bitlines
36
and
37
, equalization transistor
35
and BLSA
38
are configured identically to their corresponding elements from the first open bitline pair. In a memory array, a plurality of open bitline pairs are arranged one below the other as shown in
FIG. 3
, in which all the bitlines connected to the left side of the BLSA's are part of the left sub-array and all the bitlines connected to the right side of the BLSA's are part of the right sub-array. For DRAM memories, it is necessary to precharge bitlines, through bitline precharge transistors (not shown), to a mid-point potential level prior to reading data from a DRAM memory cell connected to it. This mid-point pot

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