Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2007-09-25
2007-09-25
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S185220, C365S189050
Reexamination Certificate
active
11153188
ABSTRACT:
Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
REFERENCES:
patent: 5200922 (1993-04-01), Rao
patent: 5323353 (1994-06-01), Griffus et al.
patent: 5561629 (1996-10-01), Curd
patent: 5841712 (1998-11-01), Wendell et al.
patent: 5930169 (1999-07-01), Iwata et al.
patent: 6041007 (2000-03-01), Roeckner
patent: 6055207 (2000-04-01), Nam
patent: 6201738 (2001-03-01), Hebishima
patent: 6275443 (2001-08-01), Ingalls et al.
patent: 6282121 (2001-08-01), Cho et al.
patent: 6421757 (2002-07-01), Wang et al.
patent: 7057954 (2006-06-01), Kim
Hartono Hendrik
Louie Benjamin
Yip Aaron
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
Nguyen Tan T.
LandOfFree
Bitline exclusion in verification operation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bitline exclusion in verification operation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bitline exclusion in verification operation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3748276