Bit map addressing schemes for flash memory

Details Bit map addressing schemes for flash memory Bit map addressing schemes for flash memory

1996-04-19

1998-09-29

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518901, 36523001, 36523006, 36523008, G11C 700

Patent

active

058154434

ABSTRACT:
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

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