Bit line structure for a dynamic type semiconductor memory devic

Details Bit line structure for a dynamic type semiconductor memory devic Bit line structure for a dynamic type semiconductor memory devic

1988-11-28

1991-04-30

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Noise suppression

365149, G11C 506, G11C 1140

Patent

active

050124471

ABSTRACT:
Each of the bit lines constituting each of a plurality of bit line pairs included in a portion of a memory cell array comprises even-numbered intersecting portions. At the intersecting portion, the materials of respective bit lines are different from each other. The bit lines are formed of the same material at portions other than the intersecting portions. The intersecting portions are arranged such that one of the bit lines constituting each bit line pair neighbors one of the bit lines constituting an adjacent one of the bit line pairs for a first length and neighbors the other one of the bit lines constituting the adjacent bit line pair for a second length; and the other one of the bit lines constituting the bit line pair neighbors the one of the bit lines of the adjacent bit line pair for the first length and neighbors the other one of the bit lines of the adjacent bit line pair for the second length.

REFERENCES:
ISSCC 87/Feb. 26, 1987/Session XVI: "Microprocessors-Special Purpose", by P. W. Bosshart, C. R. Hewes, M-Chamg Change, K-Kit Chau, et al.

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