Bit-line pull-up circuit

Details Bit-line pull-up circuit Bit-line pull-up circuit

1984-12-21

1987-01-27

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

307548, G11C 1140

Patent

active

046398988

ABSTRACT:
A memory array in which a pull-up network for the bit lines includes a relatively high impedance low power dissipation static network which tends to maintain the bit lines at a given level during standby, and a relatively low impedance network which is momentarily pulsed into conduction prior to a read and/or a write cycle for quickly precharging the bit lines to the given level.

REFERENCES:
patent: 4451907 (1984-05-01), Donoghue et al.
patent: 4499559 (1985-02-01), Kurafuji

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