Bit line precharge on a column address change

Details Bit line precharge on a column address change Bit line precharge on a column address change

1985-08-05

1987-04-14

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365230, G11C 700

Patent

active

046583815

ABSTRACT:
A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. Memory cells along an enabled word line cause the bit lines to develop a voltage differential. In response to a change in the row address the bit lines are equalized and precharged. In response to a change in the column address, the bit lines are precharged without being equalized so that the developed voltage differential on the bit lines is maintained.

REFERENCES:
patent: 4346459 (1982-08-01), Sud et al.
patent: 4355377 (1982-10-01), Sud et al.
patent: 4482984 (1984-11-01), Oritani
patent: 4549101 (1985-10-01), Sood
patent: 4581718 (1986-04-01), Oishi

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