Bit line precharge in a bimos ram

Details Bit line precharge in a bimos ram Bit line precharge in a bimos ram

1988-02-01

1990-02-06

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Precharge

365177, 365190, 365208, G11C 1140

Patent

active

048993174

ABSTRACT:
In a static random access memory in which the array is comprised of MOS transistors and at least some of the peripheral circuits are comprised of bipolar transistors, the bit lines and data lines are precharged to a base to emitter voltage drop (i.e. one Vbe) below the positive power supply voltage. This increases cell stability. Additionally, Vbe varies comparatively little over process. Additionally, precharging the bit lines and data lines to a Vbe below the positive power supply voltage allows for the use of a high speed bipolar differential amplifier in its optimum operating range as the first stage sense amplifier.

REFERENCES:
patent: 4110840 (1978-08-01), Abe et al.
patent: 4386419 (1983-05-01), Yamamoto
patent: 4604533 (1986-08-01), Miyamoto et al.
patent: 4665505 (1987-05-01), Miyakawa et al.
patent: 4682200 (1987-06-01), Uchida et al.
patent: 4727517 (1988-02-01), Ueno et al.

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