Bit-line precharge current limiter for CMOS dynamic memories

Details Bit-line precharge current limiter for CMOS dynamic memories Bit-line precharge current limiter for CMOS dynamic memories

1995-03-13

1996-03-12

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Precharge

365190, 365202, G11C 1300

Patent

active

054992117

ABSTRACT:
A fault-tolerant DRAM design minimizes current flow in the even of a cross-fail. A bit-line precharge current limiter is provided for the bit-line precharge equalizer circuit. The bit-line precharge current limiter is both simple and effective, requiring very little silicon area to implement. The current limiter provides self current-limiting for defective bit-lines, without the necessity for a reference cell.

REFERENCES:
patent: 4636983 (1987-01-01), Young et al.
patent: 4730276 (1988-03-01), Waller
patent: 4998223 (1991-03-01), Akaogi
patent: 5012132 (1991-04-01), Wang
patent: 5255235 (1993-10-01), Miyatake
patent: 5270971 (1993-12-01), Muraoka et al.
patent: 5280451 (1994-01-01), Akaogi

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