Bit line load circuit for semiconductor static RAM

Details Bit line load circuit for semiconductor static RAM Bit line load circuit for semiconductor static RAM

1993-08-10

1995-05-23

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365202, 365204, 365190, G11C 700

Patent

active

054187486

ABSTRACT:
In a semiconductor static RAM which includes at least one static RAM memory cell connected to a pair of complementary bit lines and each connected to a different word line. A bit line load circuit is connected between the pair of complementary bit lines and a voltage supply potential, and a column selection circuit is connected between the pair of complementary bit lines and a pair of complementary common data bus lines coupled to an input/output data control circuit. The bit line load circuit includes a pair of precharge P-channel insulated gate field effect transistors connected between the voltage supply potential and the pair of complementary bit lines. A bit line equalizing P-channel insulated gate field effect transistor is connected between the pair of complementary bit lines. A gate of each of these P-channel transistors is connected to receive the same internal precharge signal. A pair of bit line level compensating N-channel insulated gate field effect transistors are connected in parallel to the precharge P-channel transistors, respectively, and the gate of each of the pair of bit line level compensating N-channel transistors is connected to the voltage supply potential.

REFERENCES:
patent: 4802128 (1989-01-01), Watanabe et al.
patent: 4823319 (1989-04-01), Pfennings
patent: 5007023 (1991-04-01), Kim et al.
patent: 5047984 (1991-09-01), Monden

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