Bit line equalizing control circuit of a semiconductor...

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Reexamination Certificate

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C365S202000, C365S230030

Reexamination Certificate

active

07978551

ABSTRACT:
A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit line equalizing signal is delayed and enabled, a bit line equalizing selecting unit that generates a bit line equalizing detection signal in response to a plurality of mat select signals and the control signal, and a driver that receives the bit line equalizing detection signal to generate the bit line equalizing signal.

REFERENCES:
patent: 5487044 (1996-01-01), Kawaguchi et al.
patent: 5946251 (1999-08-01), Sato et al.
patent: 6222782 (2001-04-01), Chon
patent: 1020010055884 (2001-07-01), None
patent: 1020080003050 (2008-07-01), None

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