Bit line equalize circuit of semiconductor memory device

Details Bit line equalize circuit of semiconductor memory device Bit line equalize circuit of semiconductor memory device

1998-01-21

1999-08-31

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Precharge

365154, 365190, G11C 1140

Patent

active

059462515

ABSTRACT:
A memory cell data is read/written to a memory cell by utilizing the base current of a bipolar transistor having its emitter coupled to a bit line. When activated, a bit line precharge circuit precharges the bit line to a level of a built-in voltage between the emitter and the base of the memory cell bipolar transistor. When bit lines in a pair are lowered in potential from the H level to the L level, the base electrode node potential of the bipolar transistor is never changed to a negative potential by capacitance coupling, and conduction of an access transistor and destruction of memory cell data are prevented. A semiconductor memory device is implemented which does not cause data destruction and can stably operate at high speed even under a low power supply voltage.

REFERENCES:
patent: 4868628 (1989-09-01), Simmons
patent: 5289409 (1994-02-01), Reinschmidt
patent: 5483483 (1996-01-01), Choi et al.
patent: 5764565 (1998-06-01), Sato et al.

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