Bit line dummy core-cell and method for producing a bit line...

Details Bit line dummy core-cell and method for producing a bit line... Bit line dummy core-cell and method for producing a bit line...

2008-07-01

2008-07-01

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S207000

Reexamination Certificate

active

07394682

ABSTRACT:
A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

REFERENCES:
patent: 5850364 (1998-12-01), Ueno
patent: 6172925 (2001-01-01), Bloker
patent: 6335891 (2002-01-01), Wilkins

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