Bit line driver

Static information storage and retrieval – Read/write circuit – Precharge

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365190, G11C 700

Patent

active

048021288

ABSTRACT:
In a bit line driver for MOS memory units of a microcomputer, which is connected between a pair of complementary bit lines and provided with an equalizing MOS transistor, a pair of active-load MOS transistors and a pair of clamping MOS transistors are connected separately to the complementary bit lines, and further the area of the clamping MOS transistors is determined to be about three times greater than that of the active-load transistors. An increase in the area of the clamping MOS transistors serves to decrease the internal resistance thereof, so that the clamping operation can be improved. A decrease in area of the active-load MOS transistor serves to increase the internal resistance, so that the access time can be improved. In addition, the driver can operate stably in response to a low power clock pulse.

REFERENCES:
patent: 4112506 (1978-09-01), Zibu
patent: 4355377 (1982-10-01), Sud et al.
patent: 4479202 (1984-10-01), Uchida
patent: 4494221 (1985-01-01), Hardee et al.
patent: 4494221 (1985-01-01), Hardee
K. Hardee et al., "A 30 ns 64K CMOS RAM", 1984 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 216-217.

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