Bit addressable programming arrangement

Details Bit addressable programming arrangement Bit addressable programming arrangement

1985-05-31

1988-01-12

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, 365242, G11C 700

Patent

active

047195983

ABSTRACT:
A programming arrangement for programmable matrices which have a plurality of memory elements, input terminals for addressing the elements, input/output terminals for receiving a signal from an addressed element when the matrix is operated in a READ mode, and for receiving programming signals when the matrix is operated in a PROGRAM mode, and a programming current supply source. The arrangement provides for controlling the flow of programming current to any of the memory elements by application of programming signals to less than all of the input/output terminals. A programming decoder is provided having inputs connected to the input/output terminals and outputs connected to apparatus for controlling the flow of programming current. The decoder expands the programming utility of the input/output terminals and, thus, allows for programming of redundant rows of columns, programmable output polarity apparatus, and other special matrix features via the available device pins. The need for additional device pins and/or increased use of supervoltage or "zenered" pin techniques is avoided.

REFERENCES:
patent: 3689712 (1971-09-01), Dennard
patent: 3740723 (1973-06-01), Beausoleil et al.
patent: 3753235 (1973-08-01), Daughton et al.
patent: 3906461 (1975-09-01), Cappon
patent: 4276617 (1981-06-01), Le
patent: 4374430 (1983-02-01), Higuchi
patent: 4628480 (1986-12-01), Floyd

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