Bistable logic circuit using field effect transistors with a low

Details Bistable logic circuit using field effect transistors with a low Bistable logic circuit using field effect transistors with a low

1982-08-16

1985-04-23

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365175, 365154, G11C 1140

Patent

active

045133980

ABSTRACT:
The logic circuit comprises two field effect transistors in series, whose gates are connected to the supply voltage by a first load. The source of the first field effect transistor is connected to earth. The drain of the second field effect transistor is connected on the one hand to the supply voltage by a second load and to the gate of a third field effect transistor, whose drain is connected to the supply voltage and whose source is connected to the common point constituted by the drain of the first field effect transistor and the source of the second field effect transistor via a Schottky diode.

REFERENCES:
patent: 4394589 (1983-07-01), Pham et al.
patent: 4402127 (1983-09-01), Pham et al.
patent: 4442509 (1984-04-01), Herndon
"High-Speed Low-Power Logic IC's Using Quasi-Normally-Off GaA's MESFET" by Gerard Nuzillat et al., IEEE, Journal of Solid-State Circuits, vol. SC-16, No. 3, Jun. 1981, pp. 226-232.

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