Bist for parallel testing of on chip memory

Details Bist for parallel testing of on chip memory Bist for parallel testing of on chip memory

2005-08-23

2005-08-23

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000

Reexamination Certificate

active

06934205

ABSTRACT:
A processor assisted memory BIST to identify detective memory addresses. The processor generates the address to be tested and the BIST generates the test data used to test the memory. Data is written to an read from memory. The read data is compared with the test data. If a mismatch occurs, the BIST generates an interrupt to identify the processor. Since the processor generated the address, the defective memory address is identified. The defective memory address can subsequently be replaced with redundant memory cells.

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