Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-26
2003-03-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S350000, C438S313000
Reexamination Certificate
active
06528375
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bipolar transistor having a polysilicon emitter and, in particular, to a bipolar device formed utilizing a single polysilicon layer and a tilted ion-implanted link base region that may readily be incorporated into existing CMOS processes.
2. Description of the Related Art
The majority of integrated circuit designs employ some form of digital signal processing. These conventional logic structures dictate the use of complementary MOS (CMOS) device architectures. In the pursuit of enhanced performance and greater flexibility, IC designers have increasingly relied upon circuits that combine both bipolar and MOS transistor technologies. For maximum process efficiency, a polysilicon bipolar transistor should be formed in a process flow that shares as many processing steps as possible with a standard CMOS process flow. However, creating a process flow that successfully integrates bipolar and MOS architectures can pose a significant challenge.
FIG. 1A
shows a cross-sectional view of a conventional NPN bipolar transistor device which includes a diffused polysilicon emitter structure formed from a single polysilicon layer. Conventional single-poly NPN bipolar transistor
100
lies within N-well
102
formed in P-type silicon
104
. Conventional single-poly bipolar transistor
100
is electrically isolated from the effects of adjacent semiconductor devices by inter-device isolation structures
106
.
NPN transistor
100
further includes a buried N+ collector layer
108
connected to collector contact
110
by N+ sinker structure
112
. Collector contact
110
may be conveniently formed during the source/drain implant steps of an associated CMOS process. Collector contact
110
and sinker
112
are electrically insulated from the remainder of transistor
100
by intra-device isolation structure
114
.
Bipolar transistor
100
also includes P-type base
116
having a P+ base contact
118
. Base
116
consists of intrinsic base region
116
a
and extrinsic base region
116
b
. As used in this patent application, the term “intrinsic base” refers to that portion of the base directly underneath the collector. The term “extrinsic base” refers to that portion of the base region of the bipolar transistor which is not directly underneath the collector.
Base
116
may be formed within N-well
102
during implantation of dopant to form the lightly doped drain (pldd) regions of associated CMOS devices. Base contact
118
may be formed during the source/drain implant of associated CMOS devices.
Bipolar transistor
100
further includes diffused polysilicon emitter structure
122
. Emitter
122
includes a polysilicon contact component
122
a
and a diffused single crystal component
122
b
. Polysilicon contact component
122
a
may be formed from the same N-type polysilicon layer used to create the gates of associated CMOS devices. Diffused single crystal component
122
b
is formed by thermal diffusion of N-type dopant from polysilicon contact component
122
a
into base
116
.
Conventional single-poly bipolar transistor
100
also includes an overlying dielectric material
124
.
While the conventional single-poly bipolar transistor shown in
FIG. 1A
is useful in many applications, it suffers from the disadvantage of exhibiting a relatively high base resistance.
FIG. 1B
shows an enlarged cross-sectional view of an edge portion of the emitter base junction of the device of FIG.
1
A. During operation of bipolar transistor
100
, the bulk of the charge traveling between base contact
118
and intrinsic base
116
a
must traverse conductive path
126
.
Because the overlying interconnect must make contact with both polysilicon emitter component
122
a
and base contact region
118
, regions
116
a
and
118
must be separated to ensure electrical isolation between the contacts. Therefore, conductive path
126
traverses a relatively long distance. The length of path
126
in turn creates high electrical resistance.
The elevated high base resistance acts to degrade device performance. In particular, equation (I) determines the maximum frequency of switching of the transistor:
(
I
)
f
MAX
=
f
T
/
(
8
π
C
JBC
R
B
)
,
where
:
f
MAX
=
frequency
at
which
unilateral
power
gain
is
unity
f
T
=
unity
gain
cutoff
frequency
C
JBC
=
base
-
collector
junction
capacitance
R
B
=
base
resistance
(
intrinsic
+
extrinsic
)
Thus, a higher overall base resistance will reduce the switching frequency of the transistor. A low f
MAX
is particularly problematic given the extremely rapid switching frequencies demanded by modern, high-speed digital applications.
In order to reduce base resistance and thereby overcome this disadvantage, device engineers have implemented a double-polysilicon bipolar transistor design.
FIG. 2A
shows a cross-sectional view of a conventional double-poly NPN bipolar transistor device.
Double-poly NPN bipolar transistor
200
lies within N-well
202
formed within P-type silicon
204
. Conventional double-poly bipolar transistor
200
is electrically isolated from the effects of adjacent semiconductor devices by inter-device isolation structures
206
.
Bipolar transistor
200
includes a buried N+ collector layer
208
connected to collector contact
210
by N+ sinker structure
212
. Collector contact
210
may conveniently be formed during the source/drain implant steps of an associated CMOS process. Collector contact
210
and sinker
212
are electrically isolated from remainder of transistor
200
by intra-device isolation structure
214
.
Bipolar transistor
200
further includes a doped base layer
216
, which includes an intrinsic base region
216
a
. Diffused polysilicon base
218
overlies and is separated from doped base layer
216
by a first dielectric layer
219
. Diffused polysilicon base
218
includes a polysilicon contact component
218
a
and a diffused single crystal silicon component
218
b.
Polysilicon base contact
218
a
is formed from a P-type polysilicon layer. Single crystal base component
218
b
is formed by diffusion of P type dopant from polysilicon base contact
218
a
into doped base layer
216
.
Bipolar transistor
200
further features diffused polysilicon emitter structure
222
which is formed over and separated from polysilicon base
218
a
by second dielectric layer
224
. Diffused polysilicon emitter structure
222
includes polysilicon emitter contact component
222
a
and single crystal diffused emitter component
222
b.
Polysilicon emitter contact
222
a
is formed from a second doped polysilicon layer of N-type conductivity, as could be used to form the gates of associated CMOS transistors Single crystal emitter component
222
b
is formed by diffusion of N-type dopant from polysilicon component
222
a
into doped base layer
216
.
FIG. 2B
is an enlarged view of an edge portion of the emitter/base junction of the device of FIG.
2
A.
FIG. 2B
reveals that because single crystal base component
218
b
is self-aligned to single crystal emitter component
222
b
, regions
218
b
and
222
b
are separated by only the width of second dielectric layer
224
(typically less than 0.4 &mgr;m). This configuration is made possible by the presence of polysilicon base contact component
218
a
, and single crystal base component
218
b
, which provide highly doped, low-resistance conductive path
226
to intrinsic base
216
a.
While the conventional double-poly bipolar transistor structure addresses significant performance disadvantages of the conventional single-poly bipolar transistor, this design suffers from a serious disadvantage in the form of more complex processing. Specifically, the double-poly bipolar transistor depicted in
FIG. 2A
requires addi
Le Dung A
National Semiconductor Corporation
Nelms David
Stallman & Pollock LLP
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