Bipolar ESD protection structure

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S362000, C257S363000, C257S355000, C257S356000, C257S360000, C361S111000, C361S058000, C438S338000, C438S342000

Reexamination Certificate

active

06891230

ABSTRACT:
The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements. The emitter is contained within the footprint of the collector elements, and enables containment of device size, therefore minimizing device capacitance characteristics important in high speed circuit design. Other embodiments of the invention use variations in the structure of the common contiguous emitter conductor as well as different base conductor structure layouts.

REFERENCES:
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patent: 5341005 (1994-08-01), Canclini
patent: 5528189 (1996-06-01), Khatibzadeh
patent: 5850095 (1998-12-01), Chen et al.
patent: 6472286 (2002-10-01), Yu
patent: 6720625 (2004-04-01), Yu
Yu, Tai Lee, Co-Pending U.S. Appl. No. 10/790,919 filed Mar. 2, 2004.
Yu, Tai Lee, Response Under Rule 1.111 filed on Oct. 21, 2004 in Co-Pending U.S. Appl. No. 10/790,919.
J. Chen et al., “Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits”, IEEE Jrnl 1996, 0-7803-2753- 5/96, pp. 227-232.

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