Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
Patent
1996-03-29
1999-06-29
Santamauro, Jon
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
Field-effect transistor
326110, 257204, 257378, H03K 1908, H01L 2700
Patent
active
059173424
ABSTRACT:
A BiMOS integrated circuit includes a bipolar transistor for output pull-up; a BiMOS hybrid gate buffer section which comprises a MOS transistor for output pull-down which is longitudinally connected to the bipolar transistor, and a MOS transistor for base drive which comprises an output which is connected a base of the bipolar transistor to drive the base and a gate which is connected to an input; and a logical section which comprises at least a CMOS gate, the logical section having an output which is connected to the input; wherein the base drive MOS transistor has an input capacitance less than that of the output pull-down MOS transistor.
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Wissel, Larry, et al "A 180-ps, 220K-Circuit BICMOS ASIC Logic Chip", Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, Boston, MA, May 3-6, 1992, pp. 27.4.1-27.4.4.
El Gamal, Abbas, et al "BiNMOS: A Basic Cell for BiCMOS Sea-of-Gates", Proceedings of the IEEE 1989 Custom Integrated Circuits Conference, San Diego, CA, May 15-18, 1989, pp. 8.3.1-8.3.4.
NEC Corporation
Santamauro Jon
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