BiMIS circuit

Details BiMIS circuit BiMIS circuit

1994-03-11

1995-06-20

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 34, 326110, H03K 1901

Patent

active

054263778

ABSTRACT:
A BiMIS circuit includes a load pull-up bipolar transistor, a load pull-down bipolar transistor, a first MISFET and first and second MISFETs for driving the load pull-up bipolar transistor, and a third MISFET and a second MISFET for driving the load pull-down bipolar transistor. The second MISFET has a turn-on voltage lower than the turn-on voltage of the load pull-up bipolar transistor, and the second MISFET has a turn-on voltage lower than the turn-on voltage of the load pull-down bipolar transistor.

REFERENCES:
patent: 4845386 (1989-07-01), Ueno
patent: 4999523 (1991-03-01), Cham et al.
patent: 5313116 (1994-05-01), Murabayashi et al.

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