Bilayer deposition to avoid unwanted interfacial reactions...

Details Bilayer deposition to avoid unwanted interfacial reactions... Bilayer deposition to avoid unwanted interfacial reactions...

2002-06-21

2004-02-24

Kang, Donghee (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S287000, C438S785000, C257S310000, C257S410000

Reexamination Certificate

active

06696332

ABSTRACT:

FIELD OF INVENTION
This invention relates generally to semiconductor devices and methods for fabricating MOSFET devices having high-k gate dielectric stacks.
BACKGROUND OF THE INVENTION
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a metal or polysilicon gate contact is energized to create an electric field within a semiconductor channel, by which current is allowed to conduct between a source region and a drain region. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. A gate dielectric is formed over the channel region, and a gate contact (e.g., metal or doped polysilicon) is formed over the gate dielectric. The gate dielectric is an insulator material, which prevents large currents from flowing from the gate into the channel when a voltage is applied to the gate contact, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner.
FIG. 1
a
illustrates a conventional semiconductor device
2
with both PMOS and NMOS transistor devices
4
and
6
, respectively. The device
2
is fabricated using conventional complimentary MOS (CMOS) processing techniques in a semiconductor substrate
8
, in which isolation structures (e.g., SiO2 field oxide (FOX) or shallow trench isolation (STI) structures)
10
are formed to separate and provide electrical isolation of the individual devices
4
and
6
from other devices and from one another. The substrate
8
is lightly doped p-type silicon with an N-well
12
formed therein under the PMOS transistor
4
. The PMOS device
4
includes two laterally spaced P-doped source/drain regions
14
a
and
14
b
with a channel region
16
located therebetween. A gate is formed over the channel region
16
comprising an insulative gate dielectric layer
20
, such as silicon dioxide (SiO2) overlying the channel
16
and a conductive polysilicon gate contact structure
22
formed over the gate dielectric layer
20
.
The NMOS device
6
includes two laterally spaced N-doped source/drain regions
24
a
and
24
b
with a channel region
26
located therebetween. A gate is formed over the channel region
26
comprising an insulative gate dielectric layer
30
, such as silicon dioxide (SiO2) overlying the channel
26
and a conductive polysilicon gate contact structure
32
formed over the gate dielectric layer
30
. Typical CMOS production processing has thusfar not adopted high-k gate dielectric layers, although such layers are being studied. Instead, the gate dielectric layer
30
of
FIG. 1
a
is typically formed through thermal oxidation of the silicon substrate
8
to form the layer
30
of SiO2.
In operation, the resistivity of the channel
26
may be controlled by the voltage applied to the gate contact
32
, by which changing the gate voltage changes the amount of current through channel
26
. The gate contact
32
and the channel
26
are separated by the gate dielectric stack
30
, which is an insulator. Thus, little or no current flows between the gate contact
32
and the channel
26
, although “tunneling” current is observed with thin dielectrics. However, the gate dielectric allows the gate voltage to induce an electric field in channel
26
, by which the channel resistance can be controlled by the applied gate voltage.
Field-effect transistors such as transistors
4
and
6
of
FIG. 1
a
are physically very small in many cases, whereby many such devices may be formed on a single-crystal silicon substrate or chip and interconnected in an integrated circuit. In the field of semiconductor device technology, there is a continuing trend toward higher device densities, and hence smaller and smaller device dimensions. Generally, device density is improved by scaling or decreasing the size of the transistors and other electrical components. At the same time, however, MOSFET devices produce an output signal proportional to the ratio of the width over the length of the channel, where the channel length is the physical distance between the source/drain regions (e.g., between regions
24
a
and
24
b
in the device
6
) and the width runs perpendicular to the length (e.g., perpendicular to the page in
FIG. 1
a
). Thus, scaling the MOSFET device
6
to make the width narrower may reduce the device output. Previously, this characteristic has been accommodated by decreasing the thickness of gate dielectric
30
, thus bringing the gate contact
32
closer to the channel
26
for the device
6
of
FIG. 1
a
. Making the gate dielectric layer
30
smaller, however, has other effects, which may lead to performance tradeoffs.
In particular, there are limitations in the use of silicon dioxide in the formation of thinner gate dielectric layers. For instance, extremely thin SiO2 layers allow for large gate tunneling leakage currents due to direct tunneling through the oxide. This problem is exacerbated by limitations in the ability to deposit such thin films with uniform thickness. Thus, it has been found that MOSFET operating parameters may change dramatically due to slight variations in gate dielectric thickness. Furthermore, thin gate dielectric layers are known to provide poor diffusion barriers to impurities. Thus, for example, extremely thin SiO2 gate dielectric layers suffer from high boron penetration into the underlying channel region during implantation of source/drain regions outlying the channel region. Consequently, recent efforts at MOSFET device scaling have focused on alternative dielectric materials which can be formed in a thicker layer than scaled silicon dioxide layers and yet still produce the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are greater than that of SiO2. The relative performance of such high-k materials is often expressed as equivalent oxide thickness (EOT), because the alternative material layer may be thicker, while providing the equivalent electrical effect of a much thinner layer of SiO2.
Referring to
FIG. 1
b
, one proposed alternative structure for applying high-k gate dielectric materials in a gate dielectric layer
30
′ is illustrated in a MOSFET device
6
′ including a layer of dielectric (e.g., oxide) material
30
a
deposited using standard deposition processing techniques, such as chemical vapor deposition (CVD) or sputtering processes. A conductive polysilicon gate contact structure
32
′ is then formed over the gate dielectric layer
30
a
. However, an undesirable (e.g., low-k) interfacial layer
30
b
is formed between the substrate
8
and the deposited oxide
30
a
. The interfacial layer
30
b
is not directly deposited, but instead is the result of oxidation of the substrate material
8
during deposition of the oxide layer
30
a.
Referring also to
FIG. 2
, a sectional TEM view is provided of a portion of an actual high-k gate structure
50
overlying a semiconductor substrate
52
. In the gate structure
50
, an interfacial layer
56
is formed during sputtering deposition of a hafnium silicon oxide dielectric layer
54
with O
2
employed in the deposition process. The deposited gate dielectric layer
54
is illustrated underlying a subsequently deposited polysilicon gate contact layer
58
. During deposition of the oxide material layer
54
, the low-k interfacial layer
56
is formed between the substrate
52
and the gate dielectric layer
54
, due to deposition process related oxidation of the substrate
52
. Thus, from
FIG. 2
it is seen that the relative thicknesses
54
a
and
56
a
of the gate dielectric and the interfacial layers, respectively, can be quite significant in practice (e.g., about 27 Å and 26 Å, respectively).
At the same time, however, the alternative materials explored thusfar a

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