Fishing – trapping – and vermin destroying
Patent
1991-03-12
1995-01-10
Maples, John S.
Fishing, trapping, and vermin destroying
437174, 437192, 437247, H01L 21441, H01L 21324
Patent
active
053806786
ABSTRACT:
A process for forming an electrical connection in a semiconductor device between an aluminum interconnect and the substrate avoids junction spiking at temperatures (1000.degree. C.-1500.degree. C.) significantly above the standard semiconductor device fabrication temperatures (<500.degree. C.). An insulating layer is formed over an upper surface of the substrate with a via formed through the insulating layer to expose a portion of the substrate to which electrical connection is to be made. A first refractory metal barrier layer is formed over the insulating layer and the exposed portion of the substrate. Preferably, the first barrier layer is TiN. A second refractory metal barrier layer is formed over the first barrier layer to provide extra thickness and to cap the first barrier layer to minimize the gas emission and enhanced optical ablation due to the first barrier layer during laser planarization, and to provide a wetting layer during and produce a desirable surface morphology after laser planarization. The second layer is preferably Ti. A metal interconnect layer is formed following the deposition of the second barrier layer without breaking vacuum. The metal interconnect layer is preferably aluminum or its alloys. The aluminum layer is annealed above the melting point of the interconnect metal in a very short time to planarize the aluminum and to flow the aluminum to fill any voids. The aluminum and barrier layers are etched to form an appropriate interconnect pattern.
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Wolf S. "Silicon Processing for the VLSI Era" vol. 2, Lattice Press Sunset Beach Calif., p. 128 1990 (no month).
Wolf, S. "Silicon Processing for the VLSI Era", vol. 2, Lattice Press, Sunset Beach, Calif. pp. 255-256, 1990 (no month).
Doan Trung T.
Yu Chang
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