Method and apparatus for designing integrated circuits for testa

Details Method and apparatus for designing integrated circuits for testa Method and apparatus for designing integrated circuits for testa

1989-10-24

1992-07-21

Smith, Jerry

Excavating

371 221, 371 251, G06F 1100

Patent

active

051329743

ABSTRACT:
The invention is a method for designing testability into an integrated circuit. This method is termed register transfer scan (RTS). The RTS method comprises two primary rules. The first rule is that every global feedback path in the functional circuit must contain at least one scannable storage element, i.e. it must be accessible such that data can be placed into it or read from it without passing the data through the functional circuitry of the chip. The second rule of the RTS method is that the controls for those storage elements that are not scannable are held inactive when data is being scanned into or out of the scannable storage elements.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 3784907 (1974-01-01), Eichelberger
patent: 4534028 (1985-08-01), Trischler
patent: 4602210 (1986-07-01), Fasang et al.
patent: 4669081 (1987-05-01), Mathewes, Jr. et al.
patent: 4916388 (1990-04-01), Sano
Williams, T. W. & Parker, K. P., Design For Testability-A Survey, Proceedings of the IEEE, vol. 71, No. 1, Jan. 1983.
Eichelberger, E. B. & Williams, T. W., A Logic Design Structure for LSI Testability, Proc. 14th Design Automation Conference, 1977, pp. 462-468.
Trischler, E., Testability Analysis and Incomplete Scan Path.
Trischler, E., Incomplete Scan Path with an Automatic Test Generation Methodology, 1980 IEEE Test Conference, Paper 7.1, pp. 153-162.
Buchanan, M. A., Scan-Design Methods Increased Testability of Standard Cells, Computer Design Magazine, Mar. 1, 1986.

Affiliated with

Also associated with

Rating

Method and apparatus for designing integrated circuits for testa does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for designing integrated circuits for testa, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for designing integrated circuits for testa will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-850409