Bidirectional logic isolation multiplexing with voltage...

Details Bidirectional logic isolation multiplexing with voltage... Bidirectional logic isolation multiplexing with voltage...

2008-07-08

2008-07-08

Lateef, Marvin M. (Department: 4146)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S083000, C326S086000, C326S062000

Reexamination Certificate

active

11484256

ABSTRACT:
Voltage level translation for open-drain circuitry is described. A logic isolation circuit includes a first buffer circuit configured for being switched between a first voltage transferable state and a first voltage non-transferable state. A first latch circuit is configured for being switched between a first reset state and a first non-reset state, the first reset state for setting the first latch circuit to a first reset condition. A second buffer circuit and second latch circuit are configured like the first buffer circuit and the first latch circuit. First and second input/output nodes are coupled to receive first and second logic level voltages, respectively. The first logic level voltage and the second logic level voltage are both for a same logic state, but the second logic level voltage is significantly greater than the first logic level voltage.

REFERENCES:
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Signetics; “8×41 Autodirectional Bus Transceiver”; Data sheet; downloaded May 11, 2006; pp. 7-17 thru 7-21.
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SanDisk Corporation; “Supporting Two SD Devices with a Single SD Bus Host Controller”; Application Note, version 1.0; Document No. 80-36-00458; Oct. 18, 2005; pp. 1-7.
Maxim; Maxim MAX 3000 family Data sheet; “+1.2V to +5.5V, ±15kV ESD-Protected, 0.1μA, 35 Mbps, 8-Channel Level Translators”; Copyright 2005 Maxim Integrated products; pp. 1-25.

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