BiCMOS process for forming double-poly MOS and bipolar transisto

Details BiCMOS process for forming double-poly MOS and bipolar transisto BiCMOS process for forming double-poly MOS and bipolar transisto

1996-02-13

1999-08-24

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438234, H01L 218238

Patent

active

059435640

ABSTRACT:
A fully complementary double-poly BiCMOS process utilizes substantially identical device architectures to form n-channel and p-channel MOS transistors, as well as npn and pnp bipolar transistors. In the double-poly process, the first layer of polysilicon is utilized to form the source and drain of the MOS transistors as well as the base and collector of the bipolar transistors. The second layer of polysilicon is then utilized to form the gate of the MOS transistors as well as the emitter of the bipolar transistors.

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