BICMOS latch/driver circuit, such as for a gate array memory cel

Details BICMOS latch/driver circuit, such as for a gate array memory cel BICMOS latch/driver circuit, such as for a gate array memory cel

1991-05-31

1994-09-13

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518911, G11C 700

Patent

active

053474872

ABSTRACT:
A BICMOS latch driver L/D is used to implement a BICMOS gate array memory cell (FIG. 2b). The memory cell includes a latch formed by cross-coupled invertors (INV1 and INV2). The driver stage is formed by an NPN transistor Q0 and an n-channel transistor MN3. The relatively stronger bipolar transistor is used to pull the output of the BICMOS latch/driver HI, while, for most applications, the relatively weaker n-channel device has sufficient strength to pull the output low. A WRITE port (WP) that interfaces to the WRITE bitline, and a READ port (RP) that interfaces to the READ bitline.

REFERENCES:
patent: 4995001 (1991-02-01), Dawson et al.
patent: 5093806 (1992-03-01), Tran

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