BICMOS device and manufacturing method thereof

Details BICMOS device and manufacturing method thereof BICMOS device and manufacturing method thereof

1991-11-18

1993-03-09

Wojciechowicz, Edward J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

437 31, 437 34, 437 41, 437 57, 257377, 257413, 257554, H01L 2702, H01L 21265

Patent

active

051929929

ABSTRACT:
A BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second polysilicon layer on the first polysilicon layer which is impurity implanted, so that the impurity doped in the second polysilicon layer is prevented from diffusing into the channel region and the voltage characteristic is prevented from changing. Emitter regions of vertical PNP and NPN bipolar transistors are self-aligned in a small chip area, and thereby the performance of the BICMOS device is improved due to the stable threshold voltage characteristic of the PMOS and NMOS transistors and high density is achieved together with improved operation speed clue to the self-alignment formation of the emitter region of the vertical PNP and NPN bipolar transistors.

REFERENCES:
patent: 5091760 (1992-02-01), Maeda et al.
patent: 5102811 (1992-04-01), Scott

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