Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-12-22
1999-05-18
Mai, Son
Static information storage and retrieval
Floating gate
Particular biasing
36518505, 3651851, 257319, G11C16/04
Patent
active
059056754
ABSTRACT:
Disclosed is a method for biasing dual row line EEPROM cells. The new biasing scheme improves the data retention lifetime of an EEPROM cell by reducing the potential difference between the control gate and the write column of the cell, which reduces the tunnel oxide electric field. In a preferred embodiment, the method involves applying bias voltages to the control gate and write column of an EEPROM cell such that the potential difference between the control gate and the right column is no more than about 0.5 volts. By biasing the cell's write column to a positive voltage, the tunnel oxide field may be significantly reduced. Moreover, the invention provides a method of selecting a write column voltage based on a control gate voltage such that the tunnel oxide field is substantially balanced in all its modes. This biasing scheme minimizes SILC and improves cell reliability.
REFERENCES:
patent: 5625211 (1997-04-01), Kowshik
patent: 5742542 (1998-04-01), Lin et al.
patent: 5761116 (1998-06-01), Li et al.
patent: 5764569 (1998-06-01), Wright
Costello John C.
Liang Minchang
Madurawe Raminda U.
Sansbury James D.
Smolen Richard G.
Altera Corporation
Mai Son
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