Bias scheme to reduce burn-in test time for semiconductor memory

Details Bias scheme to reduce burn-in test time for semiconductor memory Bias scheme to reduce burn-in test time for semiconductor memory

1998-07-22

1999-09-07

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Testing

36518527, G11C 700

Patent

active

059497262

ABSTRACT:
This invention describes a biasing scheme that reduces burn-in testing time as well as the number of cycles through the burn-in test for a semiconductor memory. The magnitude of a substrate back bias is reduced when a semiconductor memory device is taken into burn-in at a first value of an external applied voltage. When the memory device is brought out of burn-in, the substrate back bias is returned to the original operating level at a second value of the external applied voltage. The reduction of the substrate back bias allows for a higher external voltage to stress the semiconductor memory without forcing breakdown and results in a shorter test time. The burn-in test is entered at a higher magnitude of the external applied voltage than the voltage at which burn-in testing is exited. This helps to reduce the number of cycles through the burn-in test by providing a stronger external bias.

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patent: 5363333 (1994-11-01), Tsujimoto
patent: 5452253 (1995-09-01), Choi
patent: 5467356 (1995-11-01), Choi
patent: 5657282 (1997-08-01), Lee
patent: 5790465 (1998-08-01), Roh et al.

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