Electrical computers and digital data processing systems: input/ – Input/output data processing – Concurrent input/output processing and data transfer
Reexamination Certificate
1999-09-08
2003-05-13
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Concurrent input/output processing and data transfer
C710S014000, C710S031000, C710S033000, C710S038000
Reexamination Certificate
active
06564269
ABSTRACT:
BACKGROUND OF THE INVENTION
Most computer systems consist of a processor unit and a number of peripheral devices coupled to the processor unit. The peripheral devices send and receive information to and from the processor and, typically, each peripheral device is separately connected to the processor unit by an individual set of cables, with each set of cables having a number of wires. The wires may be used for transferring information from the processor unit to the peripheral, as in the case of digital pixel data transferred to an active matrix flat panel display; or, the wires may used for transferring digital information from the peripherals to the processor unit, as in the case of digital data transferred from a keyboard or mouse to the processor unit. The information may be transferred serially or in parallel, depending upon the number of wires and the communications protocol used to transmit the information.
FIG. 1
illustrates a conventional computer system
100
having a processor unit
101
and a number of peripherals coupled to the processor. The peripherals include a keyboard
102
, a mouse
103
, a display
104
, a digital camera
105
, and a pair of speakers
106
a
and
106
b.
As shown in
FIG. 1
, each of the peripherals is coupled to the processor unit through an individual cable assembly. Accordingly, the display
104
is coupled to the processor
101
through cable assembly
110
, the keyboard
102
is coupled to the processor
101
through cable assembly
111
, the mouse
103
is coupled to the processor
101
through cable assembly
112
, the digital camera
105
is coupled to the processor
101
through cable assembly
114
, and the pair of speakers
106
a
and
106
b
are coupled to the processor
101
through cable assemblies
115
a
and
115
b.
Each cable assembly may require a number of wires for communicating information back and forth between the processor
101
and the particular peripheral. As can be seen from
FIG. 1
, this conventional computer system
100
requires a large number of wires to be coupled directly to the processor
101
. This configuration is undesirable for a myriad of reasons, which should be obvious to one of ordinary skill in the art.
In order to reduce the number of wires that the user must connect to a processor unit, information may be sent to and from a hub system over a limited number of wires coupled between the processor and the hub system, where the information is then routed to the proper peripheral. The hub system may be designed as a stand alone device or it may, preferably, be implemented within one of the peripherals, with each of the other peripherals being coupled thereto.
FIG. 2
illustrates a computer system
200
having a hub system
201
coupled to a processor unit
202
. In the prior art embodiment illustrated in
FIG. 2
, the hub system
201
is implemented within a display
203
and is fully integrated within the display
203
. Additional peripherals, such as a keyboard
204
, a mouse
205
, a digital camera
206
and a pair of speakers
207
a
and
207
b
are each coupled to the hub system
201
. The hub system
201
acts as a pass through port or routing system and routes information between each of the peripherals and the processor unit
202
.
As shown in
FIG. 2
, the processor unit
202
and the hub system
201
are coupled together by two different cable assemblies
210
a
and
210
b.
Preferably, one of the cable assemblies
210
a
is used for transferring digital pixel data to the display
203
in a first direction; and, the other cable assembly
210
b
is used for communicating serial digital data back and forth between the processor unit
202
and each of the other peripherals coupled to the hub system
201
. Each cable assembly has a limited number of wires, such that this configuration is preferable over the prior art system illustrated in FIG.
1
. In a conventional computer system, cable assembly
210
a
may be configured to transmit digital pixel data to display
203
using any one of several applicable transmission protocols such as TDMS (Transition Minimized Differential Sensing), LVDS (Low Voltage Differential Sensing), or analog RGB communications. Cable assembly
210
b
may be configured to transmit digital data using any applicable digital communications protocol such as the USB (Universal Serial Bus) standards.
Digital pixel data intended to be displayed by display
203
is received over the first cable assembly
210
a,
retained, and properly processed for display by the display
203
. The serial digital data intended for any of the other peripherals is received over the second cable assembly
210
b,
passed through the hub system
201
, and routed to the proper peripheral. Accordingly, each of the other peripherals sends information to the processor unit
202
or receives information from the processor unit
202
through the hub system
201
over cable assembly
210
b;
while the display
203
receives digital pixel data over cable assembly
210
a.
In a computer system wherein TDMS communications are used for transferring digital pixel data, cable assembly
210
a
will include four twisted wire differential pairs. Alternatively, in a computer system in which LVDS communications are used for transferring digital pixel data, cable assembly
210
a
will include five twisted wire differential pairs. In TDMS communications, one twisted wire differential pair is used for each of the primary red, green and blue digital pixel data streams and the fourth twisted wire differential pair is used for transmitting a clock signal. Systems which use LVDS communications transmit digital pixel data over four dual wire pairs, with a fifth dual wire pair used for transmitting a clock signal. Twenty four bits of the digital red, green blue pixel data are transmitted over four dual wire pairs with six bits per dual wire pair in order to achieve a high transmission rate. Both TMDS and LVDS communications require a horizontal video blanking period between the transmission of digital pixel data for each line in a display, and a vertical blanking period between the transmission of each frame to be displayed.
FIG. 3
further illustrates the communication of digital pixel data over cable assembly
210
a
between processing unit
202
and display
203
in a computer system which utilizes TDMS communications. As shown, a transmitter
301
is implemented within the processor
202
for transmitting digital pixel data from the processor
202
to the display
203
. A receiver
302
is implemented within the display
203
having a hub system for receiving digital pixel data for display from the processor
202
. Cable assembly
210
a
is comprised of four twisted wire pairs, with a first twisted wire pair
305
a
used for transmitting red pixel data from the processor
202
to display
203
, a second twisted wire pair
305
b
used for transmitting green pixel data from the processor
202
to display
203
, and a third twisted pair
305
c
used for transferring blue pixel data from the processor
202
to display
203
. The fourth twisted wire pair
305
d
is used for routing a clock signal from the processor
202
to the display
203
for synchronizing the digital pixel data at the receiver
302
. Further, as shown in
FIG. 3
an enable signal DATA ENABLE is coupled to transmitter
301
. When the DATA ENABLE signal is active, digital pixel data is actively transmitted over twisted wire differential pairs
305
a
-
305
c
to display
203
.
FIG. 4
illustrates a timing diagram which shows waveforms for the forward transfer of digital pixel data to the display
203
. As shown in the timing diagram, when the DATA ENABLE signal is active, digital pixel data for a single line in the display is transferred to display
203
over twisted wire differential pairs
305
a
-
305
c.
When the DATA ENABLE signal is inactive, no valid digital pixel data is transmitted over the twisted wire differential pairs
305
a
-
305
c.
Between lines this is known as the horizontal video blanking period. Between frames this is known as the ver
Farooq Mohammad
Gaffin Jeffrey
Perkins Coie LLP
Silicon Image Inc.
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