Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-11
2003-07-22
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S668000, C257S712000, C257S713000, C257S737000, C257S738000, C257S774000, C257S777000, C438S612000, C438S668000
Reexamination Certificate
active
06596620
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to substrates for ball grid array semiconductor devices, and more specifically to via structures for solder ball connections.
BRIEF DESCRIPTION OF PRIOR ART
The demand for reduced size and increased complexity of electronic components has driven the industry to produce smaller and more complex integrated circuits (ICs). These same trends have forced the development of IC packages having smaller footprints, higher lead counts, and better electrical and thermal performance. At the same time, these IC packages are required to meet accepted industry standards.
Ball grid array (BGA) packages were developed to meet the demand for packages having higher lead counts and smaller footprints. A BGA package is typically a square package with terminals, in the form of an array of solder balls, protruding from the bottom of the package. These terminals are designed to be mounted on a plurality of pads located on the surface of a printed circuit board, or other interconnection substrate.
For many applications such as an increasing number of portable electronic systems (cellular phones, disk drives, pagers, etc.) even BGA packages are too large. In response, another class of packages has been developed to address many of the small size and improved performance issues. This class is referred to as chip scale packages or CSP. Chip scale packages are so called because the total package area is similar to, or not much larger than the size of the IC chip itself. Chip scale packages are similar to BGAs in that typically solder ball terminals are disposed underneath the package area. One CSP design, such as the Texas Instruments Micro Star™ package illustrated in
FIG. 1
, includes a semiconductor chip
10
connected by wire bonds
11
to a flexible tape substrate
12
, and the assemblage is overmolded with a plastic encapsulant
18
. Solder balls
17
are attached through vias
15
in the substrate
12
to metallized traces
16
on the chip side surface
121
of the substrate to provide the means for contact to the next level of interconnections. Another example is the Motorola SLICC and JACS-Pak devices, which include a flip chip attached to an organic substrate.
One might expect that in order to maintain the expected performance and reliability, these more complex and smaller packages would result in a cost increase. However, this is not the case, and instead, cost to both the manufacturer and the user are under significant downward pressure. As a result, the designs and processes are kept as simple as possible in an attempt to maintain high yields, low cost, and provide user-friendly assemblages.
In the fabrication of substrates for semiconductor packages having solder ball, rather than leaded contacts, vias are formed to create passages through the substrate to the opposing side, and are used to make electrical connection between the chip and the next level of interconnection, typically a printed wiring board. In substrates having multiple levels of conductors, vias typically are plated using any of several convenient techniques, to deposit a thin layer of metal on the interior surface of the via hole. The plated metal surface is wetted and the hole is filled by wicking action when solder paste is introduced, and/or when a solder ball is positioned over the hole and the solder is reflowed.
However, in the case of lower cost, single level metal substrates, such as the aforementioned Micro Star BGA package, through hole plating is not feasible. The low cost, single-metal substrates formed on a flex film (or alternate thin substrate material) include patterned metallization on only the chip side surface, and have an unmetallized via formed through the substrate to the opposite, or external surface. Solder paste applied on the external surface into the via attaches a solder ball to the bottom surface when reflowed, and in turn provides electrical contact with patterned conductors on the chip side surface.
While single level metal ball grid and chip size packages have become widely accepted and generally meet reliability and cost standards, a recurrent problem of electrical connection of solder balls to the package substrate persists.
In ball grid array packages having solder balls which provide the electrical connection between the packaged semiconductor device and the printed circuit board (PCB), the solder balls must be attached twice. The first soldering operation takes place during the attachment of the solder balls to the substrate during package assembly, and the second soldering operation involves reflow of the solder balls to the circuit board during device mounting. The problem of solder balls becoming disconnected occurs most significantly as the solder ball contacts are attached to the printed circuit board, or other next level of interconnection. One, or a few balls on a given packaged device which are electrically connected after package assembly may become disconnected during the second or board level reflow process. This problem of occasional lifted or electrically disconnected solder balls primarily impacts yield at board assembly, and is common to many CSP devices fabricated on flex film, as well as other substrates. The failure results in an expensive issue both to the semiconductor device manufacturer, as well as the end user.
It would be a significant advantage to the industry, both now and in the future, if a solution to the disconnected or lifted solder ball issue were identified and resolved.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above described problems of BGA solder ball interconnections becoming discontinuous during assembly on printed wiring boards are minimized, or eliminated.
It is an object of this invention to provide a chip scale or ball grid array substrate for semiconductor devices having improved printed wiring board yield after solder reflow.
It is an object of this invention to provide an improved substrate for ball grid array or Chip Scale packages which minimizes, or eliminates the problem of solder balls becoming electrically disconnecting during attachment to a printed wiring board, and it supports reliable solder ball connection between the device and printed wiring board.
It is an object of this invention to provide an improved via structure for package substrates having single level metallization, wherein the height to width ratio of the via is decreased without affecting the via density.
It is further an object that the invention will be cost effective, without requiring changes in the semiconductor device manufacturing process, and only minimal changes in the substrate manufacturing process.
In order to accomplish these and other objectives and advantages, a semiconductor package substrate via structure having a solid, planar, solderable metal core extending from the chip side surface through at least about one third of the dielectric substrate thickness is provided. The solderable core, preferably comprising copper, improves the height to width ratio of the via, and the improved aspect ratio allows a solder ball to fully contact the metal core, and avoids solder pull back and electrical discontinuity during reflow assembly to the board.
REFERENCES:
patent: 6097089 (2000-08-01), Gaku et al.
patent: 6180504 (2001-01-01), Farnworth et al.
Cheng Johnny
Hsu Joyce
Skrehot Michael K.
Tran Mai-Huong
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