BGA package with traces for plating pads under the chip

Details BGA package with traces for plating pads under the chip BGA package with traces for plating pads under the chip

2008-05-21

2011-11-08

Arora, Ajay K (Department: 2892)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S108000, C438S612000, C257SE21001, C257S778000

Reexamination Certificate

active

08053349

ABSTRACT:
A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (601), when the sites can be routed for metal plating (620). The space to place a maximum number (614) of signal routing traces is opened up by interrupting the periodicity of the site array from the edge (602) of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.

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