Basic cell architecture for structured application-specific...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

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11189026

ABSTRACT:
A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

REFERENCES:
patent: 5917342 (1999-06-01), Okamura
patent: 5923059 (1999-07-01), Gheewala
patent: 5977574 (1999-11-01), Schmitt et al.
patent: 6166560 (2000-12-01), Ogura et al.
patent: 2002/0167334 (2002-11-01), Nakaizumi
“Design Considerations for Regular Fabrics”, Sherlekar, ISPD '04, Apr. 18-21, 2004, pp. 97-102.

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