Base current reversal SRAM memory cell and method

Details Base current reversal SRAM memory cell and method Base current reversal SRAM memory cell and method

2001-01-08

2002-12-03

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S206000, C438S207000

Reexamination Certificate

active

06489192

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to memory circuits and in particular to improved static random access memory cells.
BACKGROUND OF THE INVENTION
Random access memory (“RAM”) cell densities have increased dramatically with each generation of new designs and have served as one of the principal technology drivers for ultra large scale integration (“ULSI”) in integrated circuit (“IC”) manufacturing. The area required for each memory cell in a memory array partially determines the capacity of a memory IC. This area is a function of the number of elements in each memory cell and the size of each of the elements. State-of-the-art memory cells for gigabit memory ICs using dynamic RAM (“DRAM”) technology have cell areas approaching six minimum feature dimensions squared, or 6F
2
, where F represents a minimum feature size for photolithographically-defined features. Static RAM (“SRAM”) densities, while increasing less dramatically than densities for DRAM technologies, have nevertheless also increased substantially.
A traditional six-device SRAM cell contains a pair of cross-coupled inverters, forming a latch circuit having two stable states. The minimum memory cell size attainable for this type of SRAM is approximately 120F
2
, as described in “CMOS Technology for 1.8V and Beyond,” by Jack Y. -C. Sun, 1997 Int. Symp. on VLSI Tech., Syst. and Apps., Digest of Tech. Papers, pp. 293-297. Achieving further size reduction requires a new mechanism of memory cell operation.
Tunnel diodes have also been employed to provide negative differential resistance for SRAM cell operation. U.S. Pat. No. 5,390,145, entitled “Resonance Tunnel Diode Memory”, issued to Nakasha et al., describes a memory cell using pairs of GaAs tunnel diodes coupled in series and providing memory cells having an area of about 30F
2
. “RTD-HFET Low Standby Power SRAM Gain Cell”, IEEE El. Dev. Lett., Vol. 19, No. 1 (January 1998), pp. 7-9, by J. P. A. van der Wagt et al. describes successful operation of memory cells using III-V semiconductor resonant tunnel diodes and separate read and write devices. However, GaAs devices are expensive to manufacture.
Base current reversal in bipolar transistors also can permit data storage. Base current reversal occurs when impact ionization occurring at a p-n junction between a base and a collector in the transistor results in minority carrier generation sufficient to cancel or exceed majority carrier injection from an emitter to the base. The base terminal then displays two or more stable states that do not source or sink current, and the transistor may be used to store information as represented by the state of the base terminal.
FIG. 1
is a graph showing a simplified current-voltage characteristic for a storage device employing base current reversal, in accordance with the prior art.
As base voltage is increased from zero volts, base current is initially increased also, as shown in a first portion of a current-voltage characteristic
21
(to the left of a point marked “B”). A first stable state, at a point denoted “A,” where no current passes through the base terminal corresponds to a base voltage of zero volts. As the base voltage increases, the number of electrons injected into the base and then diffusing into a depleted portion of the collector increases. These electrons are accelerated through the depleted portion of the collector. At the point marked “B” on the first portion
21
of the base-emitter current-voltage characteristic, holes created through impact ionization in the collector region and that are swept into the base begin to outnumber electrons injected from the emitter in forming a base terminal current I
B
. As base-emitter voltage further increases, the number of holes created by impact ionization also increases (dashed portion of curve
21
) until the net base terminal current I
B
becomes zero at the point marked “C” in
FIG. 1
, at a base emitter voltage of slightly less than 0.6 volts. This portion
21
of the current-voltage characteristic corresponds to a base current flowing in a direction normally associated with a base current for a NPN bipolar transistor.
A second portion
23
of the current-voltage characteristic corresponds to a base current flowing in the opposite of the direction illustrated in the first portion
21
. The second portion
23
corresponds to holes being created by impact ionization at the collector-base junction of the transistor, where the holes collected by the base outnumber electrons emitted from the emitter and collected by the base. The base current becomes increasingly negative until the point marked “D” on the curve
23
. At the point marked “D,” electrons injected into the base from the emitter begin to dominate the base terminal current I
B
, and the base terminal current I
B
again becomes very small (dashed trace).
The base terminal current I
B
again becomes zero at a point marked “E” in
FIG. 1
, corresponding to a base-emitter voltage of about 0.9 volts.
As base-emitter voltage is increased even further, a third portion
25
of the current-voltage characteristic corresponds to a base terminal current I
B
flowing in the same direction as the first portion
21
. The base terminal current I
B
then behaves conventionally with further increases in base emitter voltage.
At the points “A,” “C” and “E,” the net base terminal current I
B
is zero. Significantly, the transistor is stable at these points. As a result, opening a switch coupled to the base results in the transistor staying at one of these points and allowing a state of the transistor to be determined by measuring the base-emitter voltage, (i.e., a “read” of the data stored in the transistor).
U.S. Pat. No. 5,594,683, entitled “SRAM Memory Cell Using A CMOS-Compatible High Gain Gated Lateral BJT”, issued to M. -J. Chen and T. S. Huang, describes a memory employing base current reversal for data storage.
FIG. 2
is a simplified schematic diagram of a generic memory cell
30
formed from a storage device
32
and an access element
34
, in accordance with the prior art. The storage device
32
is represented as a NPN bipolar transistor in
FIG. 2
, however, the storage device
32
may be formed from a structure corresponding to a NMOS FET and may be capable of operating as either an NPN transistor or a NMOS FET, as described in “High-Gain Lateral Bipolar Action in a MOSFET Structure” by S. Verdonckt-Vandebroek et al., IEEE Trans. El. Dev., Vol. 38, No. 11, Nov. 1991, pp.2487-2496.
The memory cell
30
is read by turning the access element
34
ON through application of a suitable signal to a word line driver
36
. A sense amplifier (not shown in
FIG. 2
) is coupled to the storage device
32
through a bit line
38
and the access element
34
.
Data can be written to the storage device
32
by applying a write pulse to a control electrode of a bit line switch
40
and also turning ON the access element
34
as described above. The data bit to be written to the storage device
32
is coupled through the bit line switch
40
to a control electrode of the storage device
32
. The access element
34
is then turned OFF, electrically isolating the storage device
32
from the bitline
38
and storing the data bit in the memory cell
30
. Compact memory cells
30
drawing as little as 1 nanoampere of standby current can be designed using this approach. However, the memory cell described in U.S. Pat. No. 5,594,683 requires an area of at least 8F
2
.
There is therefore a need for a compact and robust memory cell having reduced standby power draw requirements.
SUMMARY OF THE INVENTION
In one aspect, the present invention includes a memory cell. The memory cell is formed from semiconductor material and includes a vertical access element formed on a storage device. The storage device has a control electrode, a first current-carrying electrode coupled to a first reference voltage and a second current-carrying electrode coupled to a second reference voltage. The access element has a control electrode coupled to a first selection line, a first current-carrying

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