Barrier structure for semiconductor devices

Details Barrier structure for semiconductor devices Barrier structure for semiconductor devices

2007-03-20

2007-03-20

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S758000, C257S761000, C257S763000, C257S767000, C257SE21585

Reexamination Certificate

active

11042396

ABSTRACT:
An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

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Photograph of First Commercially-Available Chip, Sep. 29, 2003, 3 pages.
Photograph of Second Commercially-Available Chip, Jun. 27, 2003, 1 page.
Photograph of Third Commercially-Available Chip, date unknown, 2 pages.

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